intra_pred_pipeline.v

a H.264/AVC Baseline Decoder

									blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
							end
						default:			//other Intra4x4 prediction modes that needs preload
						if (blk4x4_intra_preload_counter == 3'b001)
							blk4x4_intra_calculate_counter <= 3'b100;
						else if (blk4x4_intra_calculate_counter != 0)
							blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
					endcase
				else if (trigger_blk4x4_intra_pred)
					blk4x4_intra_calculate_counter <= 3'b100;
				else if (blk4x4_intra_calculate_counter != 0)
					blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
			end
		//Chroma
		else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)
			case (Intra_chroma_predmode)
				`Intra_chroma_DC:
				if ((mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001) || (!mbAddrB_availability && trigger_blk4x4_intra_pred))
					blk4x4_intra_calculate_counter <= 3'b100;
				else if (blk4x4_intra_calculate_counter != 0)
					blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
				`Intra_chroma_Horizontal:
					if (trigger_blk4x4_intra_pred)
						blk4x4_intra_calculate_counter <= 3'b100;
					else if (blk4x4_intra_calculate_counter != 0)
						blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
				`Intra_chroma_Vertical:
					if (blk4x4_intra_preload_counter == 3'b001)
						blk4x4_intra_calculate_counter <= 3'b100;
					else if (blk4x4_intra_calculate_counter != 0)
						blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
				`Intra_chroma_Plane:	//plane
					if (blk4x4_intra_precompute_counter == 4'b0001)
						blk4x4_intra_calculate_counter <= 3'b100;
					else if (blk4x4_intra_calculate_counter != 0)
						blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
			endcase
		else 
			begin
				if (trigger_blk4x4_intra_pred)
					blk4x4_intra_calculate_counter <= 3'b100;
				else if (blk4x4_intra_calculate_counter != 0)
					blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
			end
			
	assign end_of_one_blk4x4_intra = (blk4x4_intra_calculate_counter == 3'd1)? 1'b1:1'b0;
	//----------------------------------------------------------------------------------------
	//1.Preload
	//  For intra4x4,preload_counter == 3'b010 means preload mbAddrC or mbAddrD
	//				 preload_counter == 3'b001 means preload mbAddrB
	//----------------------------------------------------------------------------------------
	wire [6:0] Intra_mbAddrB_RAM_addr_bp;
	reg [5:0] Intra_mbAddrB_RAM_addr_sp;
	reg [1:0] Intra_mbAddrB_RAM_addr_ip;
	
	wire Intra_mbAddrB_RAM_rd_for_mbAddrD;
	assign Intra_mbAddrB_RAM_rd_for_mbAddrD = (blk4x4_sum_counter == 3'b0 && 
	(blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23) &&
	mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip)? 1'b1:1'b0;
	
	assign Intra_mbAddrB_RAM_rd = ((blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1) || Intra_mbAddrB_RAM_rd_for_mbAddrD)? 1'b1:1'b0;
	
	//	base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr
	assign Intra_mbAddrB_RAM_addr_bp = (Intra_mbAddrB_RAM_rd)? ((blk4x4_rec_counter > 15)? ((blk4x4_rec_counter > 19)? 7'd66:7'd44):0):0;
	
	//	shift pointer,x2 for chroma,x4 for luma
	always @ (Intra_mbAddrB_RAM_rd_for_mbAddrD or Intra_mbAddrB_RAM_rd or mb_num_h or 
		blk4x4_rec_counter or Intra4x4_predmode or blk4x4_intra_preload_counter)
		if (Intra_mbAddrB_RAM_rd_for_mbAddrD)
			Intra_mbAddrB_RAM_addr_sp <= (blk4x4_rec_counter < 16)? {mb_num_h,2'b0}:{1'b0,mb_num_h,1'b0};
		else if (Intra_mbAddrB_RAM_rd)
			begin
				if (blk4x4_rec_counter < 16)
					Intra_mbAddrB_RAM_addr_sp <= ((Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left 
					|| Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter == 5 
					&& blk4x4_intra_preload_counter == 3'b011)?	//read for mbAddrC
						{(mb_num_h + 1),2'b0}:{mb_num_h,2'b0};	
				else
					Intra_mbAddrB_RAM_addr_sp <= {1'b0,mb_num_h,1'b0};
			end
		else
			Intra_mbAddrB_RAM_addr_sp <= 0;
			
	//	pointer for relative address of each 4x4 block inside a MB
	always @ (Intra_mbAddrB_RAM_rd or blk4x4_rec_counter or blk4x4_intra_preload_counter or 
		mb_type_general[3:2] or Intra4x4_predmode or Intra_mbAddrB_RAM_rd_for_mbAddrD)
		if (blk4x4_rec_counter < 16 && Intra_mbAddrB_RAM_rd)	//luma
			begin 
				if (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1)
					begin 
						if (mb_type_general[3:2] == 2'b10)	//Intra16x16
							case (blk4x4_intra_preload_counter)
								3'b101:Intra_mbAddrB_RAM_addr_ip <= 0;
								3'b100:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
								3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
								3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
								default:Intra_mbAddrB_RAM_addr_ip <= 0;
							endcase
						else								//Intra4x4
							begin 
								if (blk4x4_intra_preload_counter == 3'b010)			//For mbAddrB
									case (blk4x4_rec_counter)
										0:Intra_mbAddrB_RAM_addr_ip <= 0;
										1:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
										4:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
										5:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
										default:Intra_mbAddrB_RAM_addr_ip <= 0;
									endcase
								else if (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left 
									|| Intra4x4_predmode == `Intra4x4_Vertical_Left)	//For mbAddrC
									case (blk4x4_rec_counter)
										0:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
										1:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
										4:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
										5:Intra_mbAddrB_RAM_addr_ip <= 2'b00;
										default:Intra_mbAddrB_RAM_addr_ip <= 0;
									endcase
								else												//For mbAddrD
									case (blk4x4_rec_counter)
										1:Intra_mbAddrB_RAM_addr_ip <= 2'b00;
										4:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
										5:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
										default:Intra_mbAddrB_RAM_addr_ip <= 0;
									endcase
							end
					end
				else if (Intra_mbAddrB_RAM_rd_for_mbAddrD)
					Intra_mbAddrB_RAM_addr_ip <= 2'b11;
				else
					Intra_mbAddrB_RAM_addr_ip <= 0;
			end
		else if (Intra_mbAddrB_RAM_rd)							//chroma
			Intra_mbAddrB_RAM_addr_ip <= (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1)? {1'b0,~blk4x4_intra_preload_counter[0]}:2'b01; 
		else	
			Intra_mbAddrB_RAM_addr_ip <= 0;
	
	//	pointer for each 4x4 block
	assign Intra_mbAddrB_RAM_rd_addr  = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip;
	
	//----------------------------------------------------------------------------------------	
	//2.Precomputation
	// 			 For Intra16x16 Luma Plane								
	//	cycle11: x1 + x3  |							
	//  cycle10: x2 + x5  |
	//  cycle9 : x4 + x6  |
	//  cycle8 : x8 + x7  | Vertical,V				    For Intra Chroma Plane
	//  cycle7 : calculate c					   cycle7: x1 + x3  |
	//	cycle6 : x1 + x3  |						   cycle6: x2 + x4	| Vertical,V
	//  cycle5 : x2 + x5  |						   cycle5: calculate c
	//  cycle4 : x4 + x6  |						   cycle4: x1 + x3	|
	//  cycle3 : x8 + x7  | Horizontal,H	   	   cycle3: x2 + x4	| Horizontal,H
	//  cycle2 : calculate a & b				   cycle2 : calculate a & b
	//  cycle1 : seed							   cycle1 : seed
	//----------------------------------------------------------------------------------------
	//	2.1 precomputation for HV:
	reg [14:0] plane_HV_prev_in;
	reg [7:0] plane_HV_A1,plane_HV_A2,plane_HV_B1,plane_HV_B2;
	reg [1:0] plane_HV_shifter1_len,plane_HV_shifter2_len;
	reg plane_HV_mux1_sel,plane_HV_mux2_sel;
	reg plane_HV_Is7;
	wire [14:0] plane_HV_out;
	reg [14:0] plane_HV_out_reg;
	
	plane_HV_precomputation plane_HV_precomputation (
		.prev_in(plane_HV_prev_in),
		.A1(plane_HV_A1),
		.A2(plane_HV_A2),
		.B1(plane_HV_B1),
		.B2(plane_HV_B2),
		.shifter1_len(plane_HV_shifter1_len),
		.shifter2_len(plane_HV_shifter2_len),
		.mux1_sel(plane_HV_mux1_sel),
		.mux2_sel(plane_HV_mux2_sel),
		.Is7(plane_HV_Is7),
		.HV_out(plane_HV_out)
		);
	always @ (blk4x4_intra_precompute_counter or mb_type_general[2] or blk4x4_rec_counter or plane_HV_out_reg 
		or Intra_mbAddrA_reg0  or Intra_mbAddrA_reg1  or Intra_mbAddrA_reg2  or Intra_mbAddrA_reg3  
		or Intra_mbAddrA_reg4  or Intra_mbAddrA_reg5  or Intra_mbAddrA_reg6  or Intra_mbAddrA_reg7 
		or Intra_mbAddrA_reg8  or Intra_mbAddrA_reg9  or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11 
		or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
		or Intra_mbAddrB_reg0  or Intra_mbAddrB_reg1  or Intra_mbAddrB_reg2  or Intra_mbAddrB_reg3  
		or Intra_mbAddrB_reg4  or Intra_mbAddrB_reg5  or Intra_mbAddrB_reg6  or Intra_mbAddrB_reg7 
		or Intra_mbAddrB_reg8  or Intra_mbAddrB_reg9  or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 
		or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
		or Intra_mbAddrD_window)
		//Intra16x16 plane
		if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0)
			case (blk4x4_intra_precompute_counter)
				11,6:	// x1,x3
				begin
					plane_HV_prev_in <= 0;		plane_HV_Is7 <= 1'b0;
					plane_HV_A1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg8 :Intra_mbAddrB_reg8;
					plane_HV_A2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg6 :Intra_mbAddrB_reg6;
					plane_HV_B1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg10:Intra_mbAddrB_reg10;	
					plane_HV_B2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg4 :Intra_mbAddrB_reg4;
					plane_HV_shifter1_len <= 0;	plane_HV_shifter2_len <= 2'b01;
					plane_HV_mux1_sel <= 1'b0;	plane_HV_mux2_sel <= 1'b0;
				end	
				10,5 :	// x2,x5
				begin
					plane_HV_prev_in <= plane_HV_out_reg;	plane_HV_Is7 <= 1'b0;
					plane_HV_A1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg9 :Intra_mbAddrB_reg9;		
					plane_HV_A2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg5 :Intra_mbAddrB_reg5;
					plane_HV_B1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg12:Intra_mbAddrB_reg12;	
					plane_HV_B2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg2 :Intra_mbAddrB_reg2;
					plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b10;
					plane_HV_mux1_sel <= 1'b1;      plane_HV_mux2_sel <= 1'b0;
				end
				9,4 :	// x4,x6
				begin
					plane_HV_prev_in <= plane_HV_out_reg;	plane_HV_Is7 <= 1'b0;
					plane_HV_A1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg11:Intra_mbAddrB_reg11;	
					plane_HV_A2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg3 :Intra_mbAddrB_reg3;
					plane_HV_B1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg13:Intra_mbAddrB_reg13;	
					plane_HV_B2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg1 :Intra_mbAddrB_reg1;
					plane_HV_shifter1_len <= 2'b10; plane_HV_shifter2_len <= 2'b10;
					plane_HV_mux1_sel <= 1'b1;      plane_HV_mux2_sel <= 1'b1;
				end
				8,3 :	// x8,x7
				begin
					plane_HV_prev_in <= plane_HV_out_reg;		plane_HV_Is7 <= 1'b1;
					plane_HV_A1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg15:Intra_mbAddrB_reg15;	
					plane_HV_A2 <= Intra_mbAddrD_window;
					plane_HV_B1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg14:Intra_mbAddrB_reg14;	
					plane_HV_B2 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg0 :Intra_mbAddrB_reg0;
					plane_HV_shifter1_len <= 2'b11; plane_HV_shifter2_len <= 2'b11;
					plane_HV_mux1_sel <= 1'b1;      plane_HV_mux2_sel <= 1'b0;
				end
				default:
				begin
					plane_HV_prev_in <= 0;	plane_HV_Is7 <= 0;
					plane_HV_A1 <= 0;	plane_HV_A2 <= 0;	plane_HV_B1 <= 0;	plane_HV_B2 <= 0;
					plane_HV_shifter1_len <= 0;	plane_HV_shifter2_len <= 0;
					plane_HV_mux1_sel <= 0;     plane_HV_mux2_sel <= 0;
				end
			endcase						 
		//Chroma Cb/Cr plane
		else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)
			case (blk4x4_intra_precompute_counter)
				7,4:	//x1,x3
				begin
					plane_HV_prev_in <= 0;		plane_HV_Is7 <= 1'b0;
					plane_HV_A1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg4:Intra_mbAddrB_reg4;
					plane_HV_A2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg2:Intra_mbAddrB_reg2;
					plane_HV_B1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg6:Intra_mbAddrB_reg6;	
					plane_HV_B2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg0:Intra_mbAddrB_reg0;
					plane_HV_shifter1_len <= 0;	plane_HV_shifter2_len <= 2'b01;