intra_pred_pipeline.v

a H.264/AVC Baseline Decoder

//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : [e-mail]
// File      : Intra_pred_pipeline.v
// Generated : Aug 4, 2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Intra16x16,Intra4x4 prediction pipeline
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module Intra_pred_pipeline (clk,reset_n,mb_type_general,blk4x4_rec_counter,
	trigger_blk4x4_intra_pred,mb_num_v,mb_num_h,blk4x4_sum_counter,NextMB_IsSkip,
	Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
	
	Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
	Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
	Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
	Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
	
	Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
	Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
	Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
	Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
	Intra_mbAddrD_window,
		
	Intra4x4_predmode,blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,
	blk4x4_intra_calculate_counter,end_of_one_blk4x4_intra,
	blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability,mbAddrC_availability,
	main_seed,plane_b_reg,plane_c_reg,
	Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_rd_addr
	);
	input clk,reset_n;
	input [3:0] mb_type_general;
	input [4:0] blk4x4_rec_counter;
	input trigger_blk4x4_intra_pred;
	input [3:0] mb_num_v,mb_num_h;
	input [2:0] blk4x4_sum_counter;
	input NextMB_IsSkip;
	input [1:0] Intra16x16_predmode;
	input [63:0] Intra4x4_predmode_CurrMb;
	input [1:0] Intra_chroma_predmode;
	
	input [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
	input [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
	input [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
	input [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
	
	input [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
	input [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
	input [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
	input [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
	input [7:0] Intra_mbAddrD_window;
	
	output [3:0] Intra4x4_predmode;
	output [2:0] blk4x4_intra_preload_counter;
	output [3:0] blk4x4_intra_precompute_counter;
	output [2:0] blk4x4_intra_calculate_counter;
	output end_of_one_blk4x4_intra;
	output blkAddrA_availability,blkAddrB_availability;
	output mbAddrA_availability,mbAddrB_availability,mbAddrC_availability;
	output [15:0] main_seed;
	output [11:0] plane_b_reg,plane_c_reg;
	output Intra_mbAddrB_RAM_rd;
	output [6:0] Intra_mbAddrB_RAM_rd_addr;
	
	reg [3:0] Intra4x4_predmode;
	reg [2:0] blk4x4_intra_preload_counter;
	reg [3:0] blk4x4_intra_precompute_counter;
	reg [2:0] blk4x4_intra_calculate_counter;
	
	reg [11:0] plane_b_reg,plane_c_reg;
	wire Intra_mbAddrB_RAM_rd;
	wire [6:0] Intra_mbAddrB_RAM_rd_addr;
	wire end_of_one_blk4x4_intra;
	wire blkAddrA_availability,blkAddrB_availability;
	wire mbAddrA_availability,mbAddrB_availability;
	
	//----------------------------------------------------------------------------------------
	//Intra4x4 prediction mode for current 4x4 block
	//----------------------------------------------------------------------------------------
	always @ (Intra4x4_predmode_CurrMb or blk4x4_rec_counter or mb_type_general)
		if (mb_type_general == `MB_Intra4x4)
			case (blk4x4_rec_counter)
				0 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[3:0]; 
				1 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[7:4];
				2 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[11:8];
				3 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[15:12];
				4 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[19:16];
				5 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[23:20];
				6 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[27:24];
				7 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[31:28];
				8 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[35:32];
				9 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[39:36];
				10:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[43:40];
				11:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[47:44];
				12:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[51:48];
				13:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[55:52];
				14:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[59:56];
				15:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[63:60];
				default:Intra4x4_predmode <= 4'b1111;	
			endcase
		else
			Intra4x4_predmode <= 4'b1111;
	
	//availability for intra4x4 predmode = Intra4x4_DC only
	assign blkAddrA_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC && 
	blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8 ||
	blk4x4_rec_counter == 10) && mb_num_h == 0))? 1'b0:1'b1;
	
	assign blkAddrB_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC && 
	blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 || 
	blk4x4_rec_counter == 5) && mb_num_v == 0))? 1'b0:1'b1; 
	
	//availability for whole intra predicted MB (both intra16x16 & intra4x4)
	//assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0;
	//assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0;
	assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0;
	assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0;
	assign mbAddrC_availability = (mb_type_general[3] && mb_num_v != 0 && mb_num_h != 10)? 1'b1:1'b0;
	
	//----------------------------------------------------------------------------------------
	//Intra prediction step control counter
	//---------------------------------------------------------------------------------------- 
	//1.Preload upper pels counter
	always @ (posedge clk)
		if (reset_n == 1'b0)
			blk4x4_intra_preload_counter <= 0;
		else if (trigger_blk4x4_intra_pred)
			begin
				//Chroma
				if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20))
					case (Intra_chroma_predmode)
						`Intra_chroma_DC			  :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b011:3'b000;
						`Intra_chroma_Horizontal:blk4x4_intra_preload_counter <= 3'b000;	
						`Intra_chroma_Vertical  :blk4x4_intra_preload_counter <= 3'b011;	
						`Intra_chroma_Plane     :blk4x4_intra_preload_counter <= 3'b011;	
					endcase
				//Luma
				//	Intra16x16
				else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter == 0)
					case (Intra16x16_predmode)
						`Intra16x16_Vertical  :blk4x4_intra_preload_counter <= 3'b101;
						`Intra16x16_Horizontal:blk4x4_intra_preload_counter <= 3'b000;	
						`Intra16x16_DC        :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b101:3'b000;
						`Intra16x16_Plane     :blk4x4_intra_preload_counter <= 3'b101;	
					endcase
				//	Intra4x4
				else if (mb_type_general[3:2] == 2'b11 && (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1
					|| blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5))	
					case (Intra4x4_predmode)
						`Intra4x4_Vertical           :blk4x4_intra_preload_counter <= 3'b010;		
						`Intra4x4_Horizontal         :blk4x4_intra_preload_counter <= 3'b000;		
						`Intra4x4_DC                 :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b010:3'b000;
						`Intra4x4_Diagonal_Down_Left :blk4x4_intra_preload_counter <= 3'b011;	//need mbAddrC			
						`Intra4x4_Diagonal_Down_Right:blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD	
						`Intra4x4_Vertical_Right     :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD	
						`Intra4x4_Horizontal_Down    :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD	
						`Intra4x4_Vertical_Left      :blk4x4_intra_preload_counter <= 3'b011;	//need mbAddrC	
						`Intra4x4_Horizontal_Up      :blk4x4_intra_preload_counter <= 3'b000;		
					endcase
			end
		else if (blk4x4_intra_preload_counter != 0)
			blk4x4_intra_preload_counter <= blk4x4_intra_preload_counter - 1;
		
	//2.Precomputation for plane mode counter
	always @ (posedge clk)
		if (reset_n == 1'b0)
			blk4x4_intra_precompute_counter <= 0;
		//Intra16x16 plane mode: 10 cycle + 1 cycle (seed)
		else if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_preload_counter == 3'b001)
			blk4x4_intra_precompute_counter <= 4'b1011;
		//Chroma8x8 plane mode: 6 cycle + 1 cycle (seed)
		else if ((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_preload_counter == 3'b001)
			blk4x4_intra_precompute_counter <= 4'b0111;
		else if (blk4x4_intra_precompute_counter != 0)
			blk4x4_intra_precompute_counter <= blk4x4_intra_precompute_counter - 1;
	
	//3.Intra prediction calculation counter
	always @ (posedge clk)
		if (reset_n == 1'b0)
			blk4x4_intra_calculate_counter <= 0;
		//Intra16x16 Luma
		else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
			begin
				if (blk4x4_rec_counter == 0)
					case (Intra16x16_predmode)
						`Intra16x16_Vertical:	
						if (blk4x4_intra_preload_counter == 3'b001)
							blk4x4_intra_calculate_counter <= 3'b100;
						else if (blk4x4_intra_calculate_counter != 0)
							blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
						`Intra16x16_Horizontal:	
						if (trigger_blk4x4_intra_pred)
							blk4x4_intra_calculate_counter <= 3'b100;
						else if (blk4x4_intra_calculate_counter != 0)
							blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;	
						`Intra16x16_DC:
						if (mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001)
							blk4x4_intra_calculate_counter <= 3'b100;
						else if (!mbAddrB_availability && trigger_blk4x4_intra_pred)
							blk4x4_intra_calculate_counter <= 3'b100;
						else if (blk4x4_intra_calculate_counter != 0)
							blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
						`Intra16x16_Plane:
						if (blk4x4_intra_precompute_counter == 4'b0001)
							blk4x4_intra_calculate_counter <= 3'b100;
						else if (blk4x4_intra_calculate_counter != 0)
							blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
					endcase
				else
					begin
						if (trigger_blk4x4_intra_pred)
							blk4x4_intra_calculate_counter <= 3'b100;
						else if (blk4x4_intra_calculate_counter != 0)
							blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
					end
			end
		//Intra4x4 Luma
		else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
			begin
				if (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || 
					blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5)
					case (Intra4x4_predmode)
						`Intra4x4_Horizontal,`Intra4x4_Horizontal_Up://Intra4x4 prediction modes do NOT need preload
						if (trigger_blk4x4_intra_pred)
							blk4x4_intra_calculate_counter <= 3'b100;
						else if (blk4x4_intra_calculate_counter != 0)
							blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
						`Intra4x4_DC:	//Intra4x4 prediction modes may or may NOT need preload
						if (mbAddrB_availability == 1'b1)	//need reload
							begin
								if (blk4x4_intra_preload_counter == 3'b001)
									blk4x4_intra_calculate_counter <= 3'b100;
								else if (blk4x4_intra_calculate_counter != 0)
									blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
							end
						else								//do not need reload
							begin
								if (trigger_blk4x4_intra_pred)
									blk4x4_intra_calculate_counter <= 3'b100;
								else if (blk4x4_intra_calculate_counter != 0)