df_pipeline.v

a H.264/AVC Baseline Decoder

	DF_edge_counter_TD == 6'd12 || DF_edge_counter_TD == 6'd13 || DF_edge_counter_TD == 6'd20 ||
	DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd29 ||
	DF_edge_counter_TD == 6'd36 || DF_edge_counter_TD == 6'd37 || DF_edge_counter_TD == 6'd44 ||
	DF_edge_counter_TD == 6'd45);
	
	assign Is_p_from_buf0 =       (DF_edge_counter_TD == 6'd1  || DF_edge_counter_TD == 6'd5  ||
	DF_edge_counter_TD == 6'd10 || DF_edge_counter_TD == 6'd14 || DF_edge_counter_TD == 6'd17 ||
	DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd26 || DF_edge_counter_TD == 6'd30 ||
	DF_edge_counter_TD == 6'd33 || DF_edge_counter_TD == 6'd38 || DF_edge_counter_TD == 6'd41 ||
	DF_edge_counter_TD == 6'd46);
	
	assign Is_p_from_buf1 =       (DF_edge_counter_TD == 6'd6  || DF_edge_counter_TD == 6'd9  ||
	DF_edge_counter_TD == 6'd15 || DF_edge_counter_TD == 6'd22 || DF_edge_counter_TD == 6'd25 ||
	DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || DF_edge_counter_TD == 6'd47);
	
	assign Is_p_from_buf2 =       (DF_edge_counter_TD == 6'd3  || DF_edge_counter_TD == 6'd11 ||
	DF_edge_counter_TD == 6'd19 || DF_edge_counter_TD == 6'd27 || DF_edge_counter_TD == 6'd35 ||
	DF_edge_counter_TD == 6'd43);	
	
	assign Is_p_from_buf3 =       (DF_edge_counter_TD == 6'd7  || DF_edge_counter_TD == 6'd23);
	
	reg [7:0] p0,p1,p2,p3;
	always @ (Is_p_from_mbAddrA or Is_p_from_mbAddrB or Is_p_from_buf0 or Is_p_from_buf1 or 
		Is_p_from_buf2 or Is_p_from_buf3 or one_edge_counter_TD or
		DF_mbAddrA_RF_dout or DF_mbAddrB_RAM_dout or 
		buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or 
		buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3)
		case ({Is_p_from_mbAddrA,Is_p_from_mbAddrB,Is_p_from_buf0,Is_p_from_buf1,Is_p_from_buf2,Is_p_from_buf3})
			6'b100000:{p0,p1,p2,p3} <= DF_mbAddrA_RF_dout;
			6'b010000:{p0,p1,p2,p3} <= DF_mbAddrB_RAM_dout;
			6'b001000:	case (one_edge_counter_TD)
							2'b00:{p0,p1,p2,p3} <= buf0_0;
							2'b01:{p0,p1,p2,p3} <= buf0_1;
							2'b10:{p0,p1,p2,p3} <= buf0_2;
							2'b11:{p0,p1,p2,p3} <= buf0_3;
						endcase
			6'b000100:	case (one_edge_counter_TD)
							2'b00:{p0,p1,p2,p3} <= buf1_0;
							2'b01:{p0,p1,p2,p3} <= buf1_1;
							2'b10:{p0,p1,p2,p3} <= buf1_2;
							2'b11:{p0,p1,p2,p3} <= buf1_3;
						endcase
			6'b000010:	case (one_edge_counter_TD)
							2'b00:{p0,p1,p2,p3} <= buf2_0;
							2'b01:{p0,p1,p2,p3} <= buf2_1;
							2'b10:{p0,p1,p2,p3} <= buf2_2;
							2'b11:{p0,p1,p2,p3} <= buf2_3;
			 			endcase
			6'b000001:	case (one_edge_counter_TD)
							2'b00:{p0,p1,p2,p3} <= buf3_0;
							2'b01:{p0,p1,p2,p3} <= buf3_1;
							2'b10:{p0,p1,p2,p3} <= buf3_2;
							2'b11:{p0,p1,p2,p3} <= buf3_3;
			 			endcase 
			default:{p0,p1,p2,p3} <= 0;
		endcase
			 
	//q0 ~ q3
	wire Is_q_from_buf0;
	wire Is_q_from_buf1;
	wire Is_q_from_buf2;
	wire Is_q_from_buf3;
	
	assign Is_q_from_buf0 = (DF_edge_counter_TD == 6'd4  || DF_edge_counter_TD == 6'd12  ||
	DF_edge_counter_TD == 6'd20 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd36 ||
	DF_edge_counter_TD == 6'd44);
	
	assign Is_q_from_buf1 = (DF_edge_counter_TD == 6'd8  || DF_edge_counter_TD == 6'd13  ||
	DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd29 || DF_edge_counter_TD == 6'd37 ||
	DF_edge_counter_TD == 6'd45);
	
	assign Is_q_from_buf2 = (DF_edge_counter_TD == 6'd5  || DF_edge_counter_TD == 6'd14  ||
	DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd30 || DF_edge_counter_TD == 6'd38 ||
	DF_edge_counter_TD == 6'd46);
	
	assign Is_q_from_buf3 = (DF_edge_counter_TD == 6'd9  || DF_edge_counter_TD == 6'd15  ||
	DF_edge_counter_TD == 6'd25 || DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 ||
	DF_edge_counter_TD == 6'd47);	
	
	reg [7:0] q0,q1,q2,q3;
	always @ (Is_q_from_buf0 or Is_q_from_buf1 or Is_q_from_buf2 or Is_q_from_buf3 or 
		rec_DF_RAM_dout or one_edge_counter_TD or DF_edge_counter_TD or 
		buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or 
		buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3)
		case ({Is_q_from_buf0,Is_q_from_buf1,Is_q_from_buf2,Is_q_from_buf3})
			4'b1000:case (one_edge_counter_TD)
						2'b00:{q3,q2,q1,q0} <= buf0_0;
						2'b01:{q3,q2,q1,q0} <= buf0_1;
						2'b10:{q3,q2,q1,q0} <= buf0_2;
						2'b11:{q3,q2,q1,q0} <= buf0_3;
					endcase
			4'b0100:case (one_edge_counter_TD)
						2'b00:{q3,q2,q1,q0} <= buf1_0;
						2'b01:{q3,q2,q1,q0} <= buf1_1;
						2'b10:{q3,q2,q1,q0} <= buf1_2;
						2'b11:{q3,q2,q1,q0} <= buf1_3;
					endcase
			4'b0010:case (one_edge_counter_TD)
						2'b00:{q3,q2,q1,q0} <= buf2_0;
						2'b01:{q3,q2,q1,q0} <= buf2_1;
						2'b10:{q3,q2,q1,q0} <= buf2_2;
						2'b11:{q3,q2,q1,q0} <= buf2_3;
			 		endcase
			4'b0001:case (one_edge_counter_TD)
						2'b00:{q3,q2,q1,q0} <= buf3_0;
						2'b01:{q3,q2,q1,q0} <= buf3_1;
						2'b10:{q3,q2,q1,q0} <= buf3_2;
						2'b11:{q3,q2,q1,q0} <= buf3_3;
			 		endcase 
			default:if (DF_edge_counter_TD != 6'd48)	{q3,q2,q1,q0} <= rec_DF_RAM_dout;
					else								{q3,q2,q1,q0} <= 0;
		endcase
				
	// |p0 - q0| < alpha
	assign absolute_TD0_a = (!disable_DF && bs_curr_TD != 0)? p0:0;
	assign absolute_TD0_b = (!disable_DF && bs_curr_TD != 0)? q0:0;
	
	// |p1 - p0| < beta
	assign absolute_TD1_a = (!disable_DF && bs_curr_TD != 0)? p0:0;
	assign absolute_TD1_b = (!disable_DF && bs_curr_TD != 0)? p1:0;
	
	// |q1 - q0| < beta
	assign absolute_TD2_a = (!disable_DF && bs_curr_TD != 0)? q0:0;
	assign absolute_TD2_b = (!disable_DF && bs_curr_TD != 0)? q1:0;
	
	// Threshold
	wire threshold;
	assign threshold = ((absolute_TD0_out < alpha) && (absolute_TD1_out < beta) && 
						(absolute_TD2_out < beta))? 1'b1:1'b0;
	
	//	Pipelined parameters
	reg [2:0] bs_curr_PRE;
	reg [5:0] DF_edge_counter_PRE;
	reg [1:0] one_edge_counter_PRE;
	reg lumaEdgeFlag_PRE,chromaEdgeFlag_PRE;
	reg [7:0] p0_PRE,p1_PRE,p2_PRE,p3_PRE;
	reg [7:0] q0_PRE,q1_PRE,q2_PRE,q3_PRE;
	reg [5:0] indexA_PRE;
	reg [7:0] alpha_PRE,beta_PRE;
	always @ (posedge gclk_DF or negedge reset_n)
		if (reset_n == 1'b0)
			begin
				bs_curr_PRE 		 <= 0;
				DF_edge_counter_PRE  <= 6'd48;
				one_edge_counter_PRE <= 2'd3;
				lumaEdgeFlag_PRE 	 <= 0;
				chromaEdgeFlag_PRE 	 <= 0;
				indexA_PRE <= 0;
				alpha_PRE  <= 0;
				beta_PRE   <= 0;
				p0_PRE <= 0;	p1_PRE <= 0;	p2_PRE <= 0;	p3_PRE <= 0;
				q0_PRE <= 0;	q1_PRE <= 0;	q2_PRE <= 0;	q3_PRE <= 0;
			end
		else 
			begin
				bs_curr_PRE 		<= (threshold)? bs_curr_TD:0;
				DF_edge_counter_PRE	<= DF_edge_counter_TD;
				one_edge_counter_PRE<= one_edge_counter_TD;
				lumaEdgeFlag_PRE 	<= (threshold)? lumaEdgeFlag_TD:0;
				chromaEdgeFlag_PRE 	<= (threshold)? chromaEdgeFlag_TD:0;
				indexA_PRE <= (threshold)? indexA:0;
				alpha_PRE  <= (threshold)? alpha:0;
				beta_PRE   <= (threshold)? beta:0;
				p0_PRE <= p0;	p1_PRE <= p1;	p2_PRE <= p2;	p3_PRE <= p3;
				q0_PRE <= q0;	q1_PRE <= q1;	q2_PRE <= q2;	q3_PRE <= q3;
			end	
	//---------------------------------------------------------------------
	//3.PRE: Precomputation
	//---------------------------------------------------------------------
	wire [7:0] absolute_PRE0_a,absolute_PRE0_b;
	wire [7:0] absolute_PRE1_a,absolute_PRE1_b;
	wire [7:0] absolute_PRE2_a,absolute_PRE2_b;
	wire [7:0] absolute_PRE0_out,absolute_PRE1_out,absolute_PRE2_out;
	
	absolute absolute_PRE0 (.a(absolute_PRE0_a),.b(absolute_PRE0_b),.out(absolute_PRE0_out));
	absolute absolute_PRE1 (.a(absolute_PRE1_a),.b(absolute_PRE1_b),.out(absolute_PRE1_out));
	absolute absolute_PRE2 (.a(absolute_PRE2_a),.b(absolute_PRE2_b),.out(absolute_PRE2_out));
		
	// |p2 - p0| < beta
	assign absolute_PRE0_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p2_PRE:0;
	assign absolute_PRE0_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p0_PRE:0;
	
	// |q2 - q0| < beta
	assign absolute_PRE1_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q2_PRE:0;
	assign absolute_PRE1_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q0_PRE:0;
	
	// |p0 - q0| < alpha >> 2 + 2
	assign absolute_PRE2_a = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? p0_PRE:0;
	assign absolute_PRE2_b = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? q0_PRE:0;
	
	wire p2_m_p0_less_beta,q2_m_q0_less_beta,p0_m_q0_less_alpha_shift;
	assign p2_m_p0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0:
								((absolute_PRE0_out < beta_PRE)? 1'b1:1'b0);
	assign q2_m_q0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0:
								((absolute_PRE1_out < beta_PRE)? 1'b1:1'b0);
	assign p0_m_q0_less_alpha_shift = (!lumaEdgeFlag_PRE || bs_curr_PRE != 4)? 1'b0:
								((absolute_PRE2_out < ((alpha_PRE >> 2) + 2))? 1'b1:1'b0);
	// bs = 1 ~ 3
	reg [4:0] c1;
	always @ (bs_curr_PRE or indexA_PRE)
		if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)
			case (bs_curr_PRE)
				3'd1:
				if 		(indexA_PRE < 23)	c1 <= 5'd0;
				else if (indexA_PRE < 33)	c1 <= 5'd1;
				else if (indexA_PRE < 37)	c1 <= 5'd2;
				else if (indexA_PRE < 40)	c1 <= 5'd3;
				else if (indexA_PRE < 43)	c1 <= 5'd4;
				else 
					case (indexA_PRE)
						6'd43:c1 <= 5'd5;	6'd44,6'd45:c1 <= 5'd6;
						6'd46:c1 <= 5'd7;	6'd47:c1 <= 5'd8;	6'd48:c1 <= 5'd9;
						6'd49:c1 <= 5'd10;	6'd50:c1 <= 5'd11;	6'd51:c1 <= 5'd13;
						default:c1 <= 0;
					endcase
				3'd2:
				if 		(indexA_PRE < 21)	c1 <= 5'd0;
				else if (indexA_PRE < 31)	c1 <= 5'd1;
				else if (indexA_PRE < 35)	c1 <= 5'd2;
				else if (indexA_PRE < 38)	c1 <= 5'd3;
				else 
					case (indexA_PRE)
						6'd38,6'd39:c1 <= 5'd4;					
						6'd40,6'd41:c1 <= 5'd5;
						6'd42:c1 <= 5'd6;	6'd43:c1 <= 5'd7;	6'd44,6'd45:c1 <= 5'd8;
						6'd46:c1 <= 5'd10;	6'd47:c1 <= 5'd11;	6'd48:c1 <= 5'd12;
						6'd49:c1 <= 5'd13;	6'd50:c1 <= 5'd15;	6'd51:c1 <= 5'd17;
						default:c1 <= 5'd0;
					endcase
				3'd3:
				if 		(indexA_PRE < 17)	c1 <= 5'd0;
				else if (indexA_PRE < 27)	c1 <= 5'd1;
				else if (indexA_PRE < 31)	c1 <= 5'd2;
				else if (indexA_PRE < 34)	c1 <= 5'd3;
				else if (indexA_PRE < 37)	c1 <= 5'd4;
				else 
					case (indexA_PRE)
						6'd37:c1 <= 5'd5;	6'd38,6'd39:c1 <= 5'd6;
						6'd40:c1 <= 5'd7;	6'd41:c1 <= 5'd8;	6'd42:c1 <= 5'd9;	6'd43:c1 <= 5'd10;
						6'd44:c1 <= 5'd11;	6'd45:c1 <= 5'd13;	6'd46:c1 <= 5'd14;	6'd47:c1 <= 5'd16;
						6'd48:c1 <= 5'd18;	6'd49:c1 <= 5'd20;	6'd50:c1 <= 5'd23;	6'd51:c1 <= 5'd25;
						default:c1 <= 5'd0;
					endcase
				default:c1 <= 0;
			endcase
		else 
			c1 <= 0; 
			
	reg [4:0] c0;
	always @ (bs_curr_PRE or lumaEdgeFlag_PRE or c1 or p2_m_p0_less_beta or q2_m_q0_less_beta)
		if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)
			begin
				if (lumaEdgeFlag_PRE)	//filter luma edge
					c0 <= (  p2_m_p0_less_beta &&  q2_m_q0_less_beta)? (c1 + 2):
						  ((!p2_m_p0_less_beta && !q2_m_q0_less_beta)? c1:(c1+1));
				else			   		//filter chroma edge
					c0 <= c1 + 1;
	   		end
		else
			c0 <= 0;  
	
	//delta_0i = [(q0 - p0) << 2 + (p1 - q1) + 4] >> 3 : P151 (8-334) of H.264/AVC standard 2003
	wire [8:0] delta_0i;
	wire need_delta_0i;
	wire [8:0]  q0_m_p0; 		//p0 - q0
	wire [11:0] delta_0i_tmp;	//[(p0 - q0) << 2 + (p1 - q1) + 4]	
	assign need_delta_0i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4);
	assign q0_m_p0 = 	  (need_delta_0i)? ({1'b0,q0_PRE} + {1'b1,~p0_PRE} + 1):0;
	assign delta_0i_tmp = (need_delta_0i)? ({q0_m_p0[8],q0_m_p0,2'b0} + p1_PRE + {4'b1111,~q1_PRE} + 5):0;
	assign delta_0i = delta_0i_tmp[11:3];
	
	
	//delta p1i = [(p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)] >> 1	: P152 (8-341) of H.264/AVC standard 2003
	//delta q1i = [(q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)] >> 1	: P152 (8-343) of H.264/AVC standard 2003
	wire [8:0] delta_p1i,delta_q1i;
	wire need_p1i;
	wire need_q1i;
	wire [8:0] p0_q0_sum; //p0+q0+1
	wire [9:0] neg_p1_shift; //-(p1 << 1)
	wire [9:0] neg_q1_shift; //-(q1 << 1)
	wire [9:0] delta_p1i_tmp;// (p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)
	wire [9:0] delta_q1i_tmp;// (q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)
	assign need_p1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta);
	assign need_q1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta);
	assign p0_q0_sum = (need_p1i || need_q1i)? ({1'b0,p0_PRE} + {1'b0,q0_PRE} + 1):0;
	assign neg_p1_shift =  (need_p1i)? ({1'b1,~p1_PRE,1'b1} + 1):0; 
	assign neg_q1_shift =  (need_q1i)? ({1'b1,~q1_PRE,1'b1} + 1):0;