df_mem_ctrl.v

a H.264/AVC Baseline Decoder

							dis_frame_RAM_wr_addr_base <= 13'd0;
						else if (DF_edge_counter_MW < 6'd45 && DF_edge_counter_MW != 40 && DF_edge_counter_MW != 42) //Cb
							dis_frame_RAM_wr_addr_base <= 13'd6336;	
						else										//Cr
							dis_frame_RAM_wr_addr_base <= 13'd7920;
					end
				else
					dis_frame_RAM_wr_addr_base <= 0;
			end
	//---------------------------------------------------------------------------------
	// dis_frame_RAM_wr_addr_x
	// Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged)
	// x position inside a frame,since every 4 horizontal pixels have been combined as 
	// a single 32bit word,thus 0 ~ 43 for luma and 0 ~ 21 for chroma
	//---------------------------------------------------------------------------------
	wire [3:0] mb_num_v_DF_m1; 
	assign mb_num_v_DF_m1 = {4{Is_mbAddrB_wr}} & (mb_num_v_DF - 1);				 
	
	reg [1:0] blk4x4_xoffset;	//0 ~ 3,xoffset for blk4x4 inside a MB 
	always @ (Is_luma_wr or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW)
		case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
			3'b100:	//Is_mbAddrA_wr
			if (Is_luma_wr)	blk4x4_xoffset <= 2'd3;
			else			blk4x4_xoffset <= 2'd1;
			3'b010:	//Is_mbAddrB_wr
			case (DF_edge_counter_MW)
				6'd5,6'd37,6'd45:blk4x4_xoffset <= 2'd0;
				6'd9,6'd38,6'd46:blk4x4_xoffset <= 2'd1;
				6'd13			:blk4x4_xoffset <= 2'd2;
				6'd14			:blk4x4_xoffset <= 2'd3;
				default			:blk4x4_xoffset <= 0;
			endcase
			3'b001:	//Is_currMB_wr
			case (DF_edge_counter_MW)
				//6'd6,6'd21,6'd23,6'd22,6'd39,6'd41,6'd47:blk4x4_xoffset <= 0;
				6'd10,6'd25,6'd27,6'd26,6'd43,6'd44	:blk4x4_xoffset <= 2'd1;
				6'd15,6'd29,6'd31,6'd33				      :blk4x4_xoffset <= 2'd2;
				6'd17,6'd30,6'd35,6'd36				      :blk4x4_xoffset <= 2'd3;
				default								              :blk4x4_xoffset <= 0;
			endcase
			default:
			if (DF_12_cycles != 4'd12)
				case (DF_12_cycles[3:2])
					2'b00		    :blk4x4_xoffset <= 0;		//buf2 -> blk22
					2'b01,2'b10	:blk4x4_xoffset <= 2'd1;	//T0 -> blk21,T1 -> blk23
					default		  :blk4x4_xoffset <= 0;
				endcase
			else
				blk4x4_xoffset <= 0;
		endcase
	
	reg [5:0] dis_frame_RAM_wr_addr_x;
	
	always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_mbAddrA_wr 
		or Is_mbAddrB_wr or Is_currMB_wr or blk4x4_rec_counter_2_raster_order[1:0]
		or mb_num_h or mb_num_h_DF_m1 or mb_num_h_DF or blk4x4_xoffset)
		if (disable_DF)
			begin
				if (Is_MB_LeftTop_wr)
					dis_frame_RAM_wr_addr_x	<= (Is_luma_wr)? ({mb_num_h,2'b0} 	  + blk4x4_rec_counter_2_raster_order[1:0]):({1'b0,mb_num_h,1'b0} + blk4x4_rec_counter_2_raster_order[0]);
				else
					dis_frame_RAM_wr_addr_x <= 0;
			end
		else
			begin
				if (Is_1st_cycle_wr)
					case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
						3'b100:	//Is_mbAddrA_wr
						dis_frame_RAM_wr_addr_x	<= (Is_luma_wr)? ({mb_num_h_DF_m1,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF_m1,1'b0} + blk4x4_xoffset);
						3'b010,3'b001:	//Is_mbAddrB_wr,Is_currMB_wr
						dis_frame_RAM_wr_addr_x	<= (Is_luma_wr)? ({mb_num_h_DF,2'b0}    + blk4x4_xoffset):({1'b0,mb_num_h_DF,1'b0}    + blk4x4_xoffset);
						
						default:		//for DF_12_cycles != 4'd12
						dis_frame_RAM_wr_addr_x <= {1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset;
					endcase
				else
					dis_frame_RAM_wr_addr_x <= 0;
			end
	//---------------------------------------------------------------------------------
	// dis_frame_RAM_wr_addr_y
	// a)Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged)
	// b)For 2,3,4 write cycles,dis_frame_RAM_wr_addr is directly +44/+22 instead of 
	//   changing dis_frame_RAM_wr_addr_y
	// c)y addr increase 1 means +44 for luma or +22 for choma
	//---------------------------------------------------------------------------------		
	reg [1:0] blk4x4_yoffset;	//0 ~ 3,yoffset for blk4x4 inside a MB 		
	always @ (Is_mbAddrA_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW)
		if (Is_mbAddrA_wr)
			case (DF_edge_counter_MW)
				6'd0,6'd32,6'd40:blk4x4_yoffset <= 2'd0;
				6'd2,6'd34,6'd42:blk4x4_yoffset <= 2'd1;
				6'd16			      :blk4x4_yoffset <= 2'd2;
				6'd18			      :blk4x4_yoffset <= 2'd3;
				default			    :blk4x4_yoffset <= 0;
			endcase
		else if (Is_currMB_wr)
			case (DF_edge_counter_MW)
				//6'd6,6'd10,6'd15,6'd17,6'd39,6'd43,6'd47:blk4x4_yoffset <= 0;
				6'd21,6'd25,6'd29,6'd30,6'd41,6'd44	:blk4x4_yoffset <= 2'd1;
				6'd23,6'd27,6'd31,6'd35				      :blk4x4_yoffset <= 2'd2;
				6'd22,6'd26,6'd33,6'd36             :blk4x4_yoffset <= 2'd3;
				default								              :blk4x4_yoffset <= 0;
			endcase
		else if (DF_12_cycles != 4'd12)
			case (DF_12_cycles[2])
				1'b0:blk4x4_yoffset <= 2'd1;	// 0 ~ 3:buf2->22; 8 ~ 11:T1->23
				1'b1:blk4x4_yoffset <= 0;		// 4 ~ 7:T0->21
			endcase	
		else
			blk4x4_yoffset <= 0;
	
	reg [7:0] dis_frame_RAM_wr_addr_y;	//y position inside a frame,0 ~ 143 for luma & 0 ~ 71 for chroma 
	always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr 
		or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_mbAddrB_wr or  Is_currMB_wr
		or blk4x4_sum_counter[1:0] or blk4x4_rec_counter_2_raster_order[4:1] 
		or mb_num_v	or mb_num_v_DF or mb_num_v_DF_m1
		or one_edge_counter_MW or blk4x4_yoffset or DF_12_cycles)
		if (disable_DF)
			begin
				if (Is_MB_LeftTop_wr)
					dis_frame_RAM_wr_addr_y <= (Is_luma_wr)?
					({mb_num_v,4'b0} 	  + {blk4x4_rec_counter_2_raster_order[3:2],2'b00} + blk4x4_sum_counter[1:0]):
					({1'b0,mb_num_v,3'b0} + {blk4x4_rec_counter_2_raster_order[1],  2'b00} + blk4x4_sum_counter[1:0]);
				else
					dis_frame_RAM_wr_addr_y <= 0;
			end
		else
			begin
				if (Is_1st_cycle_wr)
					case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
						3'b100:	//Is_mbAddrA_wr
						dis_frame_RAM_wr_addr_y <= (Is_luma_wr)?			//luma or chroma
						(({mb_num_v_DF,4'b0}      + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW):
						(({1'b0,mb_num_v_DF,3'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW);
						3'b010:	//Is_mbAddrB_wr
						dis_frame_RAM_wr_addr_y <= (Is_luma_wr)?			//luma or chroma
						(({mb_num_v_DF_m1,4'b0}      + 4'd12) + one_edge_counter_MW):
						(({1'b0,mb_num_v_DF_m1,3'b0} + 4'd4 ) + one_edge_counter_MW);
						3'b001:	//Is_currMB_wr
						dis_frame_RAM_wr_addr_y <= (Is_luma_wr)?			//luma or chroma
						(({mb_num_v_DF,4'b0} 	  + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW):
						(({1'b0,mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW);
						default:
						if (DF_12_cycles != 4'd12)
							dis_frame_RAM_wr_addr_y <= {mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0} + DF_12_cycles[1:0];
						else
							dis_frame_RAM_wr_addr_y <= 0;
					endcase
				else
					dis_frame_RAM_wr_addr_y <= 0;
			end
	
	
	wire [12:0] dis_frame_RAM_wr_addr_y_ext;	//every "y" increase will increase 44(luma) or 22(chroma) for
												//dis_frame_RAM address
	
	assign dis_frame_RAM_wr_addr_y_ext =  (Is_luma_wr)?
			//luma,  x44 = x32 + x8 + x4
			(	  {dis_frame_RAM_wr_addr_y,5'b0} + {2'b0,dis_frame_RAM_wr_addr_y,3'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0}):
			//chroma,x22 = x16 + x4 + x2
			({1'b0,dis_frame_RAM_wr_addr_y,4'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0} + {4'b0,dis_frame_RAM_wr_addr_y,1'b0});
	
	wire [13:0] dis_frame_RAM_wr_addr_tmp;
	reg [13:0] dis_frame_RAM_wr_addr_LeftTop_reg;
	reg [13:0] dis_frame_RAM_wr_addr_reg;
	reg [13:0] dis_frame_RAM_wr_addr;
	
	assign dis_frame_RAM_wr_addr_tmp = dis_frame_RAM_wr_addr_base + dis_frame_RAM_wr_addr_y_ext + dis_frame_RAM_wr_addr_x;
	always @ (posedge clk)
		if (reset_n == 1'b0)
			dis_frame_RAM_wr_addr_LeftTop_reg <= 0;
		else if (Is_MB_LeftTop_wr)
			dis_frame_RAM_wr_addr_LeftTop_reg <= dis_frame_RAM_wr_addr_tmp;
	
	always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_chroma_wr or dis_frame_RAM_wr_addr_tmp 
		or dis_frame_RAM_wr_addr_reg or blk4x4_rec_counter_2_raster_order or dis_frame_RAM_wr_addr_LeftTop_reg)
		if (disable_DF)
			begin
				if (Is_MB_LeftTop_wr)
					dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp;
				else if (Is_1st_cycle_wr)
					case (blk4x4_rec_counter_2_raster_order[4])
						1'b0:
						case (blk4x4_rec_counter_2_raster_order[3:2])
							2'b00:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0];
							2'b01:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 176;
							2'b10:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 352;
							2'b11:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 528;
						endcase
						1'b1:
						dis_frame_RAM_wr_addr <= (blk4x4_rec_counter_2_raster_order[1])?
						(dis_frame_RAM_wr_addr_LeftTop_reg + 88 + blk4x4_rec_counter_2_raster_order[0]):
						(dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[0]);
					endcase
				else if (Is_luma_wr)
					dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44;
				else if (Is_chroma_wr)
					dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22;
				else
					dis_frame_RAM_wr_addr <= 0;
			end
		else
			begin
				if (Is_1st_cycle_wr)
					dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp;
				else if (Is_luma_wr)
					dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44;
				else if (Is_chroma_wr)
					dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22;
				else
					dis_frame_RAM_wr_addr <= 0;	
			end
			
	always @ (posedge clk)
		if (reset_n == 1'b0)
			dis_frame_RAM_wr_addr_reg <= 0;
		else if (dis_frame_RAM_wr_tmp)
			dis_frame_RAM_wr_addr_reg <= dis_frame_RAM_wr_addr;

	//dis_frame_RAM_din
	wire Is_mbAddrB_t1;
	wire Is_currMB_buf0;
	wire Is_currMB_buf2;
	wire Is_currMB_buf3;
	wire Is_currMB_t1;
	assign Is_mbAddrB_t1  = (DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd38 || 
							 DF_edge_counter_MW == 6'd46);
	assign Is_currMB_buf0 = (DF_edge_counter_MW == 6'd6  || DF_edge_counter_MW == 6'd15 || 
							 DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 ||
							 DF_edge_counter_MW == 6'd47);
	assign Is_currMB_buf2 = (DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd33 || 
							 DF_edge_counter_MW == 6'd41);
	assign Is_currMB_buf3 = (DF_edge_counter_MW == 6'd26);
	assign Is_currMB_t1   = (DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd23 || 
							 DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 || 
							 DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd44); 
					
	reg [31:0] dis_frame_RAM_din; 
	always @ (disable_DF or dis_frame_RAM_wr or blk4x4_sum_counter or one_edge_counter_MW or 
		DF_12_cycles or Is_mbAddrA_real_wr or Is_mbAddrB_wr or Is_mbAddrB_t1 or Is_currMB_buf0 or 
		Is_currMB_buf2 or Is_currMB_buf3 or Is_currMB_t1 or Is_currMB_wr or 
		blk4x4_sum_PE0_out or blk4x4_sum_PE1_out or blk4x4_sum_PE2_out or blk4x4_sum_PE3_out or
		p0_MW or p1_MW or p2_MW or p3_MW or 
		buf0_0 or buf0_1 or buf0_2 or buf0_3 or  
		buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3 or 
		t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3)
		if (disable_DF && dis_frame_RAM_wr)
			begin
				if (blk4x4_sum_counter[2] == 1'b0)
					dis_frame_RAM_din <= {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out};
				else
					dis_frame_RAM_din <= 0;
			end
		else if (!disable_DF && dis_frame_RAM_wr)
			case ({Is_mbAddrA_real_wr,Is_mbAddrB_wr,Is_currMB_wr})
				3'b100:	//Is_mbAddrA_wr
				dis_frame_RAM_din <= {p0_MW,p1_MW,p2_MW,p3_MW};
				3'b010:	//Is_mbAddrB_wr
				begin
					if (Is_mbAddrB_t1)		//T1 -> mbAddrB
						case (one_edge_counter_MW)
							2'd0:dis_frame_RAM_din <= t1_0;
							2'd1:dis_frame_RAM_din <= t1_1;
							2'd2:dis_frame_RAM_din <= t1_2;
							2'd3:dis_frame_RAM_din <= t1_3;
						endcase
					else 					//T0 -> mbAddrB
						case (one_edge_counter_MW)
							2'd0:dis_frame_RAM_din <= t0_0;
							2'd1:dis_frame_RAM_din <= t0_1;
							2'd2:dis_frame_RAM_din <= t0_2;
							2'd3:dis_frame_RAM_din <= t0_3;
						endcase
				end
				3'b001:	//Is_currMB_wr
				case ({Is_currMB_buf0,Is_currMB_buf2,Is_currMB_buf3,Is_currMB_t1})
					4'b1000:	//Is_currMB_buf0
					case (one_edge_counter_MW)
						2'd0:dis_frame_RAM_din <= buf0_0;
						2'd1:dis_frame_RAM_din <= buf0_1;
						2'd2:dis_frame_RAM_din <= buf0_2;
						2'd3:dis_frame_RAM_din <= buf0_3;
					endcase
					4'b0100:	//Is_currMB_buf2
					case (one_edge_counter_MW)
						2'd0:dis_frame_RAM_din <= buf2_0;
						2'd1:dis_frame_RAM_din <= buf2_1;
						2'd2:dis_frame_RAM_din <= buf2_2;
						2'd3:dis_frame_RAM_din <= buf2_3;
					endcase
					4'b0010:	//Is_currMB_buf3
					case (one_edge_counter_MW)
						2'd0:dis_frame_RAM_din <= buf3_0;
						2'd1:dis_frame_RAM_din <= buf3_1;
						2'd2:dis_frame_RAM_din <= buf3_2;
						2'd3:dis_frame_RAM_din <= buf3_3;
					endcase
					4'b0001:	//Is_currMB_t1
					case (one_edge_counter_MW)
						2'd0:dis_frame_RAM_din <= t1_0;
						2'd1:dis_frame_RAM_din <= t1_1;
						2'd2:dis_frame_RAM_din <= t1_2;
						2'd3:dis_frame_RAM_din <= t1_3;
					endcase
					default:	//Is_currMB_t0
					case (one_edge_counter_MW)
						2'd0:dis_frame_RAM_din <= t0_0;
						2'd1:dis_frame_RAM_din <= t0_1;
						2'd2:dis_frame_RAM_din <= t0_2;
						2'd3:dis_frame_RAM_din <= t0_3;
					endcase
				endcase
				default://additional 12 cycles
				case (DF_12_cycles[3:2])
					2'b00:	//0 ~ 3,buf2 -> blk22
					case (DF_12_cycles[1:0])
						2'd0:dis_frame_RAM_din <= buf2_0;
						2'd1:dis_frame_RAM_din <= buf2_1;
						2'd2:dis_frame_RAM_din <= buf2_2;
						2'd3:dis_frame_RAM_din <= buf2_3;
					endcase
					2'b01:	//4 ~ 7,T0	-> blk21
					case (DF_12_cycles[1:0])
						2'd0:dis_frame_RAM_din <= t0_0;
						2'd1:dis_frame_RAM_din <= t0_1;
						2'd2:dis_frame_RAM_din <= t0_2;
						2'd3:dis_frame_RAM_din <= t0_3;
					endcase
					default://8 ~ 11,T1 -> blk23
					case (DF_12_cycles[1:0])
						2'd0:dis_frame_RAM_din <= t1_0;
						2'd1:dis_frame_RAM_din <= t1_1;
						2'd2:dis_frame_RAM_din <= t1_2;
						2'd3:dis_frame_RAM_din <= t1_3;
					endcase
				endcase
			endcase
		else
			dis_frame_RAM_din <= 0;
endmodule