inter_mv_decoding.v

a H.264/AVC Baseline Decoder

					2:	//4x8
					case (subMbPartIdx)
						0:begin	mvy_CurrMb1[7:0]  <= mvy;	mvy_CurrMb1[23:16] <= mvy;	end
						1:begin	mvy_CurrMb1[15:8] <= mvy;	mvy_CurrMb1[31:24] <= mvy;	end
					endcase
					3:	//4x4
					case (subMbPartIdx)
						0:mvy_CurrMb1[7:0]   <= mvy;
						1:mvy_CurrMb1[15:8]  <= mvy;
						2:mvy_CurrMb1[23:16] <= mvy;
						3:mvy_CurrMb1[31:24] <= mvy; 
					endcase
				endcase
				2:
				case (sub_mb_type)
					0:mvy_CurrMb2 <= {mvy,mvy,mvy,mvy};
					1:	//8x4
					case (subMbPartIdx)
						0:begin	mvy_CurrMb2[7:0]   <= mvy;	mvy_CurrMb2[15:8]  <= mvy;	end
						1:begin	mvy_CurrMb2[23:16] <= mvy;	mvy_CurrMb2[31:24] <= mvy;	end
					endcase
					2:	//4x8
					case (subMbPartIdx)
						0:begin	mvy_CurrMb2[7:0]  <= mvy;	mvy_CurrMb2[23:16] <= mvy;	end
						1:begin	mvy_CurrMb2[15:8] <= mvy;	mvy_CurrMb2[31:24] <= mvy;	end
					endcase
					3:	//4x4
					case (subMbPartIdx)
						0:mvy_CurrMb2[7:0]   <= mvy;
						1:mvy_CurrMb2[15:8]  <= mvy;
						2:mvy_CurrMb2[23:16] <= mvy;
						3:mvy_CurrMb2[31:24] <= mvy; 
					endcase
				endcase
				3:
				case (sub_mb_type)
					0:mvy_CurrMb3 <= {mvy,mvy,mvy,mvy};
					1:	//8x4
					case (subMbPartIdx)
						0:begin	mvy_CurrMb3[7:0]   <= mvy;	mvy_CurrMb3[15:8]  <= mvy;	end
						1:begin	mvy_CurrMb3[23:16] <= mvy;	mvy_CurrMb3[31:24] <= mvy;	end
					endcase
					2:	//4x8
					case (subMbPartIdx)
						0:begin	mvy_CurrMb3[7:0]  <= mvy;	mvy_CurrMb3[23:16] <= mvy;	end
						1:begin	mvy_CurrMb3[15:8] <= mvy;	mvy_CurrMb3[31:24] <= mvy;	end
					endcase
					3:	//4x4
					case (subMbPartIdx)
						0:mvy_CurrMb3[7:0]   <= mvy;
						1:mvy_CurrMb3[15:8]  <= mvy;
						2:mvy_CurrMb3[23:16] <= mvy;
						3:mvy_CurrMb3[31:24] <= mvy; 
					endcase
				endcase
			endcase
	//----------------------------		
	//mbAddrA write --> mvx_mbAddrA
	//----------------------------
	always @ (posedge clk)
		if (reset_n == 0)
			mvx_mbAddrA <= 0;
		else if (mb_num_h != 10)//if mb_num_h == 10,mvx_mbAddrA will be no use 
			begin
				//P_skip
				if (slice_data_state == `skip_run_duration && end_of_MB_DEC)
					mvx_mbAddrA <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]};
				//Inter16x16
				else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)
					mvx_mbAddrA <= {mvx,mvx,mvx,mvx};
				//Inter16x8
				else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0)
					case (mbPartIdx)
						0:begin	mvx_mbAddrA[15:8]  <= mvx;	mvx_mbAddrA[7:0]   <= mvx;	end
						1:begin	mvx_mbAddrA[23:16] <= mvx;	mvx_mbAddrA[31:24] <= mvx;	end
					endcase
				//Inter8x16
				else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 0)
					mvx_mbAddrA <= {mvx,mvx,mvx,mvx};
				//Inter8x8
				else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)
					case (mbPartIdx)
						1:
						case (sub_mb_type)
							0:begin	mvx_mbAddrA[15:8] <= mvx;	mvx_mbAddrA[7:0] <= mvx;	end
							1:if (subMbPartIdx == 0) mvx_mbAddrA[7:0]  <= mvx; 
							  else					 mvx_mbAddrA[15:8] <= mvx;
							2:if (subMbPartIdx == 1) begin	mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx;end
							3:if (subMbPartIdx == 1)	  mvx_mbAddrA[7:0]  <= mvx;
							  else if (subMbPartIdx == 3) mvx_mbAddrA[15:8] <= mvx;
						endcase
						3:
						case (sub_mb_type)
							0:begin	mvx_mbAddrA[23:16] <= mvx;	mvx_mbAddrA[31:24] <= mvx;	end
							1:if (subMbPartIdx == 0) mvx_mbAddrA[23:16]  <= mvx; 
							  else					 mvx_mbAddrA[31:24]  <= mvx;
							2:if (subMbPartIdx == 1) begin	mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx;end
							3:if (subMbPartIdx == 1)	  mvx_mbAddrA[23:16] <= mvx;
							  else if (subMbPartIdx == 3) mvx_mbAddrA[31:24] <= mvx;
						endcase
					endcase
			end
	always @ (posedge clk)
		if (reset_n == 0)
			mvy_mbAddrA <= 0;
		else if (mb_num_h != 10)//if mb_num_h == 10,mvy_mbAddrA will be no use 
			begin
				//P_skip 
				if (slice_data_state == `skip_run_duration && end_of_MB_DEC)
					mvy_mbAddrA <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]};
				//Inter16x16
				else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)
					mvy_mbAddrA <= {mvy,mvy,mvy,mvy};
				//Inter16x8
				else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1)
					case (mbPartIdx)
						0:begin	mvy_mbAddrA[15:8]  <= mvy;	mvy_mbAddrA[7:0]   <= mvy;	end
						1:begin	mvy_mbAddrA[23:16] <= mvy;	mvy_mbAddrA[31:24] <= mvy;	end
					endcase
				//Inter8x16
				else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 1)
					mvy_mbAddrA <= {mvy,mvy,mvy,mvy};
				//Inter8x8
				else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1)
					case (mbPartIdx)
						1:
						case (sub_mb_type)
							0:begin	mvy_mbAddrA[15:8] <= mvy;	mvy_mbAddrA[7:0] <= mvy;	end
							1:if (subMbPartIdx == 0) mvy_mbAddrA[7:0]  <= mvy; 
							  else					 mvy_mbAddrA[15:8] <= mvy;
							2:if (subMbPartIdx == 1) begin	mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy;end
							3:if (subMbPartIdx == 1)	  mvy_mbAddrA[7:0]  <= mvy;
							  else if (subMbPartIdx == 3) mvy_mbAddrA[15:8] <= mvy;
						endcase
						3:
						case (sub_mb_type)
							0:begin	mvy_mbAddrA[23:16] <= mvy;	mvy_mbAddrA[31:24] <= mvy;	end
							1:if (subMbPartIdx == 0) mvy_mbAddrA[23:16]  <= mvy; 
							  else					 mvy_mbAddrA[31:24]  <= mvy;
							2:if (subMbPartIdx == 1) begin	mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy;end
							3:if (subMbPartIdx == 1)	  mvy_mbAddrA[23:16] <= mvy;
							  else if (subMbPartIdx == 3) mvy_mbAddrA[31:24] <= mvy;
						endcase
					endcase
			end
	//-----------------------------------------		
	//mbAddrB RF read and write --> mvx_mbAddrB
	//-----------------------------------------
	always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF 
		or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v 
		or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] or mvx_CurrMb2 or mvx_CurrMb3
		or refIdxL0_A or refIdxL0_C)
		if (reset_n == 0)
			begin
				mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
				mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
				mvx_mbAddrB_din     <= 0;			
			end
		//read for DF boundary strength decoding
		else if (mv_mbAddrB_rd_for_DF) 
			begin
				mvx_mbAddrB_cs_n <= 0;	mvx_mbAddrB_rd_addr <= mb_num_h;
				mvx_mbAddrB_wr_n <= 1;	mvx_mbAddrB_wr_addr <= 0;
				mvx_mbAddrB_din	 <= 0;
			end
		//P_skip
		else if (slice_data_state == `skip_run_duration)
			begin
				if (Is_skipMB_mv_calc)		//read
					begin
						if (mb_num_v == 0)
							begin mvx_mbAddrB_cs_n <= 1;mvx_mbAddrB_rd_addr <= 0;		end
						else
							begin mvx_mbAddrB_cs_n <= 0;mvx_mbAddrB_rd_addr <= mb_num_h;end
						mvx_mbAddrB_wr_n    <= 1;
						mvx_mbAddrB_wr_addr	<= 0;
						mvx_mbAddrB_din 	<= 0;
					end
				else if (end_of_MB_DEC)	//write
					begin
						if (mb_num_v == 8)
							begin
								mvx_mbAddrB_cs_n <= 1;		mvx_mbAddrB_wr_n <= 1;
								mvx_mbAddrB_wr_addr	<= 0;	mvx_mbAddrB_din  <= 0;
							end
						else
							begin
								mvx_mbAddrB_cs_n <= 0;		mvx_mbAddrB_wr_n <= 0;
								mvx_mbAddrB_wr_addr	<= mb_num_h;
								mvx_mbAddrB_din  <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]};
							end
						mvx_mbAddrB_rd_addr <= 0;
					end
				else
					begin
						mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
						mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
						mvx_mbAddrB_din     <= 0;	
					end
			end		
		//Inter16x16
		else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) 
			begin
				if (mb_num_v == 0)		//!read,write
					begin
						mvx_mbAddrB_cs_n    <= 0;	mvx_mbAddrB_wr_n     <= 0; 
						mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= mb_num_h;	
						mvx_mbAddrB_din     <= {mvx,mvx,mvx,mvx};	
					end
				else if (mb_num_v == 8)	//read,!write
					begin
						mvx_mbAddrB_cs_n    <= 0;	mvx_mbAddrB_rd_addr  <= mb_num_h;
						mvx_mbAddrB_wr_n    <= 1;   mvx_mbAddrB_wr_addr  <= 0;
						mvx_mbAddrB_din 	<= 0;
					end
				else					//read,write
					begin
						mvx_mbAddrB_cs_n    <= 0;	mvx_mbAddrB_rd_addr  <= mb_num_h;
						mvx_mbAddrB_wr_n  	<= 0;	mvx_mbAddrB_wr_addr  <= mb_num_h;
						mvx_mbAddrB_din     <= {mvx,mvx,mvx,mvx};
					end
			end
		//Inter16x8
		else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) 
			case (mbPartIdx)
				0:	//read,!write
				begin
					if (mb_num_v == 0)	//!read,!write
						begin
							mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
							mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
							mvx_mbAddrB_din     <= 0;	
						end
					else				//read,!write
						begin
							mvx_mbAddrB_cs_n    <= 0;			mvx_mbAddrB_wr_n     <= 1; 
							mvx_mbAddrB_rd_addr <= mb_num_h;	mvx_mbAddrB_wr_addr  <= 0;	
							mvx_mbAddrB_din     <= 0;	
						end
				end
				1:	//!read,write
				begin
					if (mb_num_v == 8)	//!read,!write
						begin
							mvx_mbAddrB_cs_n    <= 0;	mvx_mbAddrB_rd_addr <= mb_num_h;
							mvx_mbAddrB_wr_n    <= 1;   mvx_mbAddrB_wr_addr  <= 0;
							mvx_mbAddrB_din 	<= 0;
						end
					else				//!read,write
						begin
							mvx_mbAddrB_cs_n    <= 0;			mvx_mbAddrB_wr_n     <= 0; 
							mvx_mbAddrB_rd_addr <= mb_num_h;	mvx_mbAddrB_wr_addr  <= mb_num_h;	
							mvx_mbAddrB_din     <= {mvx,mvx,mvx,mvx};
						end
				end
				default:
				begin
					mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
					mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
					mvx_mbAddrB_din 	<= 0;			
				end
			endcase
		//Inter8x16
		else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
			case (mbPartIdx)
				0:	//read when mbAddrA is not available for inter pred,!write
				if (refIdxL0_A == 1'b1)
					begin
						mvx_mbAddrB_cs_n    <= 0;		mvx_mbAddrB_wr_n     <= 1; 
						mvx_mbAddrB_rd_addr <= mb_num_h;mvx_mbAddrB_wr_addr  <= 0;	
						mvx_mbAddrB_din 	<= 0;	
					end
				else		
					begin
						mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
						mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
						mvx_mbAddrB_din 	<= 0;	
					end
				1:	//need read :mb_num_h == 10 && mb_num_v != 0
					//need write:mb_num_v != 8
				begin
					mvx_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1;
					mvx_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0;
					mvx_mbAddrB_rd_addr <= mb_num_h;
					mvx_mbAddrB_wr_addr <= mb_num_h;
					mvx_mbAddrB_din <=  {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};
				end
				default:
				begin
					mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
					mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
					mvx_mbAddrB_din     <= 0;			
				end
			endcase
		//8x8
		else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)	
			case (mbPartIdx)
				0,1:	//read,!write
				if (mb_num_v == 0)	//!read,!write
					begin
						mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
						mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
						mvx_mbAddrB_din     <= 0;	
					end
				else				//read,!write
					begin
						mvx_mbAddrB_cs_n    <= 0;			mvx_mbAddrB_wr_n     <= 1; 
						mvx_mbAddrB_rd_addr <= mb_num_h;	mvx_mbAddrB_wr_addr  <= 0;	
						mvx_mbAddrB_din     <= 0;	
					end
				2:		//!read,!write
				begin
					mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
					mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
					mvx_mbAddrB_din     <= 0;			
				end
				3:		//!read,write
				if (mb_num_v == 8)	//!read,!write
					begin
						mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
						mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= 0;	
						mvx_mbAddrB_din 	<= 0;			
					end
				else
					case (sub_mb_type)
						0:	//8x8
						begin
							mvx_mbAddrB_cs_n    <= 0;	mvx_mbAddrB_wr_n     <= 0; 
							mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= mb_num_h;	
							mvx_mbAddrB_din     <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};		
						end
						1: 	//8x4
						case (subMbPartIdx)
							1:
							begin
								mvx_mbAddrB_cs_n    <= 0;	mvx_mbAddrB_wr_n     <= 0; 
								mvx_mbAddrB_rd_addr <= 0;	mvx_mbAddrB_wr_addr  <= mb_num_h;	
								mvx_mbAddrB_din     <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx};			
							end
							default:
							begin
								mvx_mbAddrB_cs_n    <= 1;	mvx_mbAddrB_wr_n     <= 1; 
								mvx_mbAddrB_rd_addr <= 0;	mvx_