inter_mv_decoding.v

a H.264/AVC Baseline Decoder

//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : [e-mail]
// File      : Inter_mv_decoding.v
// Generated : May 25, 2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Decoding the motion vector x and motion vector y for Inter prediction and P_skip
// SearchRange = 16pix -> 64 -> -64 ~ + 64 -> mvd[7:0], mv[7:0], mvp[7:0]
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module Inter_mv_decoding (clk,reset_n,Is_skip_run_entry,Is_skip_run_end,
	slice_data_state,mb_pred_state,sub_mb_pred_state,mvd,
	mb_num,mb_num_h,mb_num_v,mb_type_general,sub_mb_type,end_of_MB_DEC,mbPartIdx,subMbPartIdx,compIdx,
	MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,MBTypeGen_mbAddrD,
	mvx_mbAddrB_dout,mvy_mbAddrB_dout,mvx_mbAddrC_dout,mvy_mbAddrC_dout,mv_mbAddrB_rd_for_DF,
	
	skip_mv_calc,Is_skipMB_mv_calc,mvx_mbAddrA,mvy_mbAddrA,
	mvx_mbAddrB_cs_n,mvx_mbAddrB_wr_n,mvx_mbAddrB_rd_addr,mvx_mbAddrB_wr_addr,mvx_mbAddrB_din,
	mvy_mbAddrB_cs_n,mvy_mbAddrB_wr_n,mvy_mbAddrB_rd_addr,mvy_mbAddrB_wr_addr,mvy_mbAddrB_din,
	mvx_mbAddrC_cs_n,mvx_mbAddrC_wr_n,mvx_mbAddrC_rd_addr,mvx_mbAddrC_wr_addr,mvx_mbAddrC_din,
	mvy_mbAddrC_cs_n,mvy_mbAddrC_wr_n,mvy_mbAddrC_rd_addr,mvy_mbAddrC_wr_addr,mvy_mbAddrC_din,
	mv_is16x16,
	mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,
	mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3);
	input clk,reset_n;
	input Is_skip_run_entry;
	input Is_skip_run_end;
	input [3:0] slice_data_state;
	input [2:0] mb_pred_state;
	input [1:0] sub_mb_pred_state; 
	input [7:0] mvd;
	input [6:0] mb_num;
	input [3:0] mb_num_h;
	input [3:0] mb_num_v;
	input [3:0] mb_type_general;
	input [1:0] sub_mb_type;
	input end_of_MB_DEC;
	input [1:0] mbPartIdx,subMbPartIdx;
	input compIdx;
	input [1:0] MBTypeGen_mbAddrA;
	input MBTypeGen_mbAddrD;
	input [21:0] MBTypeGen_mbAddrB_reg;
	input [31:0] mvx_mbAddrB_dout,mvy_mbAddrB_dout;
	input [7:0]  mvx_mbAddrC_dout,mvy_mbAddrC_dout;
	input mv_mbAddrB_rd_for_DF;
	
	output skip_mv_calc;
	output Is_skipMB_mv_calc;
	output [31:0] mvx_mbAddrA,mvy_mbAddrA;
	output mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n;
	output mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n;
	output [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr;
	output [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr;
	output [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din;
	output [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din;
	output mv_is16x16;
	output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
	output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
	reg mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n;
	reg mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n;
	reg [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr;
	reg [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr;
	reg [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din;
	reg [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din;
	reg mv_is16x16;
	reg [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
	reg [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
		
	reg [7:0] mvpAx,mvpAy,mvpBx,mvpBy,mvpCx,mvpCy;
	reg [31:0] mvx_mbAddrA,mvy_mbAddrA;
	wire [7:0] mvx_mbAddrD,mvy_mbAddrD;
	reg [7:0] mvpx,mvpy,mvx,mvy;
	
	reg skip_mv_calc; //This signal is of reg type and is active for one cycle after end_of_MB_DEC and before 
					  //trigger_blk4x4_inter_pred.It is used to direct motion vector prediction for skipped MB
	always @ (posedge clk)
		if (reset_n == 1'b0)
			skip_mv_calc <= 1'b0;
		else if (slice_data_state == `skip_run_duration && end_of_MB_DEC && !Is_skip_run_end)
			skip_mv_calc <= 1'b1;
		else
			skip_mv_calc <= 1'b0; 
	
	wire Is_skipMB_mv_calc;
	assign Is_skipMB_mv_calc = Is_skip_run_entry | skip_mv_calc;
	
	reg [1:0] MBTypeGen_mbAddrB;
	reg [1:0] MBTypeGen_mbAddrC;
	always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
		case (mb_num_h)
			0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
			1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
			2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
			3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
			4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
			5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
			6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
			7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
			8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
			9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
			10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
			default:MBTypeGen_mbAddrB <= 0;
		endcase
	always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
		case (mb_num_h)
			0:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[3:2];
			1:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[5:4];
			2:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[7:6];
			3:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[9:8];
			4:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[11:10];
			5:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[13:12];
			6:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[15:14];
			7:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[17:16];
			8:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[19:18];
			9:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[21:20];
			default:MBTypeGen_mbAddrC <= 0;
		endcase	  
	
	wire refIdxL0_A; //Here refIdxL0_A == 1'b1 is equal to refIdxL0_A == -1 in Page122 of H.264 2003.5 standard
	wire refIdxL0_B; //Here refIdxL0_B == 1'b1 is equal to refIdxL0_B == -1 in Page122 of H.264 2003.5 standard
	reg  refIdxL0_C; //Here refIdxL0_C == 1'b1 is equal to refIdxL0_C == -1 in Page122 of H.264 2003.5 standard
	
	assign refIdxL0_A = (
	//P_skip
	(Is_skipMB_mv_calc ||
	//Inter16x16,Inter16x8,Inter8x16 left blk
	(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_Inter16x8 || (mb_type_general == `MB_Inter8x16 && mbPartIdx == 0))) ||
	//Inter8x8,left most blk
	(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 2) && (
				sub_mb_type == 0 || 
				sub_mb_type == 1 || 
				(sub_mb_type == 2 && subMbPartIdx == 0) || 
				(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 2))))) &&
	(mb_num_h == 0 || MBTypeGen_mbAddrA[1] == 1))? 1'b1:1'b0; 
	
	assign refIdxL0_B = (
	//P_skip
	(Is_skipMB_mv_calc ||
	//Inter16x16,Inter16x8 upper blk,Inter8x16
	(mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || (mb_type_general == `MB_Inter16x8 && mbPartIdx == 0) || mb_type_general == `MB_Inter8x16)) ||
	//Inter8x8,left most blk
	(sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 1) && (
				sub_mb_type == 0 || 
				sub_mb_type == 2 || 
				(sub_mb_type == 1 && subMbPartIdx == 0) || 
				(sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 1))))) &&
	(mb_num_v == 0 || MBTypeGen_mbAddrB[1] == 1))? 1'b1:1'b0; 
	
	always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or mb_num_v or mb_num_h
		or sub_mb_type or mbPartIdx or subMbPartIdx or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD
		or refIdxL0_A or refIdxL0_B)
		//P_skip,Inter16x16
		if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16))
			begin
				if 		(mb_num_v == 0)		refIdxL0_C <= 1'b1;
				else if (mb_num_h == 10)	refIdxL0_C <= (MBTypeGen_mbAddrD    == `MB_addrD_Intra)? 1'b1:1'b0;
				else						refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
			end
		//Inter16x8
		else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8)
			begin 
				if (mbPartIdx == 0)	//upper blk
					begin
						if 		(mb_num_v == 0)		refIdxL0_C <= 1'b1;
						else if (mb_num_h == 10)	refIdxL0_C <= (MBTypeGen_mbAddrD    == `MB_addrD_Intra)? 1'b1:1'b0;
						else						refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
					end
				else 				//bottom blk
					refIdxL0_C <= refIdxL0_A;
			end
		//Inter8x16
		else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16)
			begin
				if (mbPartIdx == 0)	//left blk
					refIdxL0_C <= refIdxL0_B;
				else				//right blk
					begin
						if (mb_num_v == 0 || mb_num_h == 10)	refIdxL0_C <= refIdxL0_B;
						else									refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
					end
			end
		//Inter8x8 and below
		else if (sub_mb_pred_state == `sub_mvd_l0_s)
			case (mbPartIdx)
				2'b00:	//left-top 8x8 blk
				case (sub_mb_type)
					0:refIdxL0_C <= refIdxL0_B;
					1:refIdxL0_C <= (subMbPartIdx == 0)? refIdxL0_B:refIdxL0_A;	
					2:refIdxL0_C <= refIdxL0_B;
					3:
					case (subMbPartIdx)
						0,1:refIdxL0_C <= refIdxL0_B;
						2,3:refIdxL0_C <= 1'b0;
					endcase
				endcase
				2'b01:	//right-top 8x8 blk
				case (sub_mb_type)
					0:	//8x8
					if 		(mb_num_v == 0)	 refIdxL0_C <= 1'b1;
					else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
					else					 refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
					1:	//8x4
					if (subMbPartIdx == 0)
						begin
							if 		(mb_num_v == 0)	 refIdxL0_C <= 1'b1;
							else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
							else					 refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
						end
					else
						refIdxL0_C <= 1'b0;
					2:	//4x8
					if (subMbPartIdx == 0)	refIdxL0_C <= refIdxL0_B;
					else
						begin
							if 		(mb_num_v == 0)	 refIdxL0_C <= 1'b1;
							else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
							else					 refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
						end
					3:	//4x4
					case (subMbPartIdx)
						0:refIdxL0_C <= refIdxL0_B;
						1:
						begin
							if 		(mb_num_v == 0)	 refIdxL0_C <= 1'b1;
							else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B;
							else					 refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0;
						end
						2,3:refIdxL0_C <= 1'b0;
					endcase
				endcase
				2'b10:	//left-bottom 8x8 blk
				case (sub_mb_type)
					0:refIdxL0_C <= 1'b0;
					1:refIdxL0_C <= (subMbPartIdx == 0)? 1'b0:refIdxL0_A;	
					2:refIdxL0_C <= 1'b0;
					3:refIdxL0_C <= 1'b0;
				endcase
				2'b11:	//right-bottom 8x8 blk
				refIdxL0_C <= 1'b0;
			endcase
		else
			refIdxL0_C <= 1'b0;
	
	//-------------
	//mvpAx
	//-------------
	always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state 
		or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx 
		or mvx_mbAddrA or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
		or refIdxL0_A or refIdxL0_B or refIdxL0_C)	
		//P_skip or Inter16x16
		if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0))
			mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
		//Inter16x8
		else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) 
			begin
				if (mbPartIdx == 0)
					mvpAx <= {8{refIdxL0_B}} & mvx_mbAddrA[7:0];
				else
					mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; 
			end
		//Inter8x16
		else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0)
			begin
				if (mbPartIdx == 0)
					mvpAx <= {8{~refIdxL0_A}}  & mvx_mbAddrA[7:0];
				else
					mvpAx <= {8{refIdxL0_C}} & mvx_CurrMb0[15:8];
			end
		//Inter8x8
		else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0)	//sub_mb_pred
			case (mbPartIdx)
				0:
				case (sub_mb_type)
					0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
					1:	//8x4
					case (subMbPartIdx)
						0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
						1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8];
						default:mvpAx <= 0;
					endcase
					2:	//4x8
					case (subMbPartIdx)
						0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; 
						1:mvpAx <= mvx_CurrMb0[7:0];
						default:mvpAx <= 0;
					endcase
					3:	//4x4
					case (subMbPartIdx)
						0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0];
						1:mvpAx <= mvx_CurrMb0[7:0];
						2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8];
						3:mvpAx <= mvx_CurrMb0[23:16]; 
					endcase
				endcase
				1:
				case (sub_mb_type)
					0:mvpAx <= mvx_CurrMb0[15:8];
					1:	//8x4
					case (subMbPartIdx)
						0:mvpAx <= mvx_CurrMb0[15:8];	1:mvpAx <= mvx_CurrMb0[31:24];
						default:mvpAx <= 0;
					endcase
					2:	//4x8
					case (subMbPartIdx)
						0:mvpAx <= mvx_CurrMb0[15:8];	1:mvpAx <= mvx_CurrMb1[7:0];
						default:mvpAx <= 0;
					endcase
					3:	//4x4
					case (subMbPartIdx)
						0:mvpAx <= mvx_CurrMb0[15:8] ;	1:mvpAx <= mvx_CurrMb1[7:0];
						2:mvpAx <= mvx_CurrMb0[31:24];	3:mvpAx <= mvx_CurrMb1[23:16];	
					endcase
				endcase
				2:
				case (sub_mb_type)
					0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
					1:	//8x4
					case (subMbPartIdx)
						0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
						1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24];
						default:mvpAx <= 0;
					endcase
					2:	//4x8
					case (subMbPartIdx)
						0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
						1:mvpAx <= mvx_CurrMb2[7:0];
						default:mvpAx <= 0;
					endcase
					3:	//4x4
					case (subMbPartIdx)
						0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16];
						1:mvpAx <= mvx_CurrMb2[7:0];
						2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24];
						3:mvpAx <= mvx_CurrMb2[23:16];