hw_adc.h

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// The following are defines for the bit fields in the ADC_SAC register.
//
//*****************************************************************************
#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control.
#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling

//*****************************************************************************
//
// The following are defines for the the interpretation of the data in the
// SSFIFOx when the ADC TMLB is enabled.
//
//*****************************************************************************
#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter.
#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator.
#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator.
#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator.
#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator.
#define ADC_SSFIFO_TMLB_CNT_S   6           // Sample counter shift
#define ADC_SSFIFO_TMLB_MUX_S   0           // Input channel number shift

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_TMLB register.
//
//*****************************************************************************
#define ADC_TMLB_LB             0x00000001  // Loopback control signals

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
//
//*****************************************************************************
#define ADC_SSMUX0_MUX7_M       0x70000000  // 8th Sample Input Select.
#define ADC_SSMUX0_MUX6_M       0x07000000  // 7th Sample Input Select.
#define ADC_SSMUX0_MUX5_M       0x00700000  // 6th Sample Input Select.
#define ADC_SSMUX0_MUX4_M       0x00070000  // 5th Sample Input Select.
#define ADC_SSMUX0_MUX3_M       0x00007000  // 4th Sample Input Select.
#define ADC_SSMUX0_MUX2_M       0x00000700  // 3rd Sample Input Select.
#define ADC_SSMUX0_MUX1_M       0x00000070  // 2nd Sample Input Select.
#define ADC_SSMUX0_MUX0_M       0x00000007  // 1st Sample Input Select.
#define ADC_SSMUX0_MUX7_S       28
#define ADC_SSMUX0_MUX6_S       24
#define ADC_SSMUX0_MUX5_S       20
#define ADC_SSMUX0_MUX4_S       16
#define ADC_SSMUX0_MUX3_S       12
#define ADC_SSMUX0_MUX2_S       8
#define ADC_SSMUX0_MUX1_S       4
#define ADC_SSMUX0_MUX0_S       0

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
//
//*****************************************************************************
#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable.
#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence.
#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select.
#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable.
#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence.
#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select.
#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable.
#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence.
#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select.
#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable.
#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence.
#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select.
#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select.
#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable.
#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence.
#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select.
#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable.
#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence.
#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select.
#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable.
#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence.
#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select.
#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select.
#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable.
#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence.
#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select.

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
//
//*****************************************************************************
#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data.
#define ADC_SSFIFO0_DATA_S      0

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
//
//*****************************************************************************
#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full.
#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty.
#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer.
#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer.
#define ADC_SSFSTAT0_HPTR_S     4
#define ADC_SSFSTAT0_TPTR_S     0

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
//
//*****************************************************************************
#define ADC_SSMUX1_MUX3_M       0x00007000  // 4th Sample Input Select.
#define ADC_SSMUX1_MUX2_M       0x00000700  // 3rd Sample Input Select.
#define ADC_SSMUX1_MUX1_M       0x00000070  // 2nd Sample Input Select.
#define ADC_SSMUX1_MUX0_M       0x00000007  // 1st Sample Input Select.
#define ADC_SSMUX1_MUX3_S       12
#define ADC_SSMUX1_MUX2_S       8
#define ADC_SSMUX1_MUX1_S       4
#define ADC_SSMUX1_MUX0_S       0

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
//
//*****************************************************************************
#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select.
#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable.
#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence.
#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select.
#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable.
#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence.
#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select.
#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable.
#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence.
#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select.
#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select.
#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable.
#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence.
#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select.

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
//
//*****************************************************************************
#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data.
#define ADC_SSFIFO1_DATA_S      0

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
//
//*****************************************************************************
#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full.
#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty.
#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer.
#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer.
#define ADC_SSFSTAT1_HPTR_S     4
#define ADC_SSFSTAT1_TPTR_S     0

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
//
//*****************************************************************************
#define ADC_SSMUX2_MUX3_M       0x00007000  // 4th Sample Input Select.
#define ADC_SSMUX2_MUX2_M       0x00000700  // 3rd Sample Input Select.
#define ADC_SSMUX2_MUX1_M       0x00000070  // 2nd Sample Input Select.
#define ADC_SSMUX2_MUX0_M       0x00000007  // 1st Sample Input Select.
#define ADC_SSMUX2_MUX3_S       12
#define ADC_SSMUX2_MUX2_S       8
#define ADC_SSMUX2_MUX1_S       4
#define ADC_SSMUX2_MUX0_S       0

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
//
//*****************************************************************************
#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select.
#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable.
#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence.
#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select.
#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select.
#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable.
#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence.
#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select.
#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select.
#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable.
#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence.
#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select.
#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select.
#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable.
#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence.
#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select.

//*****************************************************************************
//
// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
//
//*****************************************************************************
#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data.
#define ADC_SSFIFO2_DATA_S      0