hw_udma.h

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#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1).
#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst.
#define UDMA_CHCTL_XFERMODE_M   0x00000007  // DMA Transfer Mode.
#define UDMA_CHCTL_XFERMODE_STOP \
                                0x00000000  // Stop
#define UDMA_CHCTL_XFERMODE_BASIC \
                                0x00000001  // Basic
#define UDMA_CHCTL_XFERMODE_AUTO \
                                0x00000002  // Auto-Request
#define UDMA_CHCTL_XFERMODE_PINGPONG \
                                0x00000003  // Ping-Pong
#define UDMA_CHCTL_XFERMODE_MEM_SG \
                                0x00000004  // Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
                                0x00000005  // Alternate Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SG \
                                0x00000006  // Peripheral Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SGA \
                                0x00000007  // Alternate Peripheral
                                            // Scatter-Gather
#define UDMA_CHCTL_XFERSIZE_S   4

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTBASE register.
//
//*****************************************************************************
#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
                                            // Pointer.
#define UDMA_ALTBASE_ADDR_S     0

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_WAITSTAT register.
//
//*****************************************************************************
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status.
#define UDMA_WAITSTAT_WAITREQ_S 0

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_SWREQ register.
//
//*****************************************************************************
#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request.
#define UDMA_SWREQ_S            0

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTSET
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set.
#define UDMA_USEBURSTSET_SET__0 0x00000000  // No Effect
#define UDMA_USEBURSTSET_SET__1 0x00000001  // Burst Only

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_USEBURSTCLR
// register.
//
//*****************************************************************************
#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear.
#define UDMA_USEBURSTCLR_CLR__0 0x00000000  // No Effect
#define UDMA_USEBURSTCLR_CLR__1 0x00000001  // Single and Burst

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKSET
// register.
//
//*****************************************************************************
#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set.
#define UDMA_REQMASKSET_SET__0  0x00000000  // No Effect
#define UDMA_REQMASKSET_SET__1  0x00000001  // Masked

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_REQMASKCLR
// register.
//
//*****************************************************************************
#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear.
#define UDMA_REQMASKCLR_CLR__0  0x00000000  // No Effect
#define UDMA_REQMASKCLR_CLR__1  0x00000001  // Clear Mask

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENASET register.
//
//*****************************************************************************
#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set.
#define UDMA_ENASET_SET__0      0x00000000  // Disabled
#define UDMA_ENASET_SET__1      0x00000001  // Enabled
#define UDMA_ENASET_CHENSET_M   0xFFFFFFFF  // Channel [n] Enable Set.
#define UDMA_ENASET_CHENSET__0  0x00000000  // No Effect
#define UDMA_ENASET_CHENSET__1  0x00000001  // Enable

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENACLR register.
//
//*****************************************************************************
#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable.
#define UDMA_ENACLR_CLR__0      0x00000000  // No Effect
#define UDMA_ENACLR_CLR__1      0x00000001  // Disable

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTSET register.
//
//*****************************************************************************
#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set.
#define UDMA_ALTSET_SET__0      0x00000000  // No Effect
#define UDMA_ALTSET_SET__1      0x00000001  // Alternate

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTCLR register.
//
//*****************************************************************************
#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear.
#define UDMA_ALTCLR_CLR__0      0x00000000  // No Effect
#define UDMA_ALTCLR_CLR__1      0x00000001  // Primary

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOSET register.
//
//*****************************************************************************
#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set.
#define UDMA_PRIOSET_SET__0     0x00000000  // No Effect
#define UDMA_PRIOSET_SET__1     0x00000001  // High Priority

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
//
//*****************************************************************************
#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear.
#define UDMA_PRIOCLR_CLR__0     0x00000000  // No Effect
#define UDMA_PRIOCLR_CLR__1     0x00000001  // Default Priority

//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ERRCLR register.
//
//*****************************************************************************
#define UDMA_ERRCLR_ERRCLR      0x00000001  // DMA Bus Error Status.

#endif // __HW_UDMA_H__