traffic.tan.qmsg

verilog HDl 交通灯的实现,而且这是有别于一般的vhdl语言

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register numb\[4\] register numb\[4\] 228.83 MHz 4.37 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 228.83 MHz between source register \"numb\[4\]\" and destination register \"numb\[4\]\" (period= 4.37 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.109 ns + Longest register register " "Info: + Longest register to register delay is 4.109 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numb\[4\] 1 REG LC_X6_Y17_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y17_N4; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.442 ns) 0.978 ns Equal2~93 2 COMB LC_X6_Y17_N0 2 " "Info: 2: + IC(0.536 ns) + CELL(0.442 ns) = 0.978 ns; Loc. = LC_X6_Y17_N0; Fanout = 2; COMB Node = 'Equal2~93'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.978 ns" { numb[4] Equal2~93 } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.114 ns) 1.521 ns Equal2~94 3 COMB LC_X6_Y17_N5 2 " "Info: 3: + IC(0.429 ns) + CELL(0.114 ns) = 1.521 ns; Loc. = LC_X6_Y17_N5; Fanout = 2; COMB Node = 'Equal2~94'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.543 ns" { Equal2~93 Equal2~94 } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.817 ns numb\[0\]~1384 4 COMB LC_X6_Y17_N6 5 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 1.817 ns; Loc. = LC_X6_Y17_N6; Fanout = 5; COMB Node = 'numb\[0\]~1384'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal2~94 numb[0]~1384 } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.458 ns) + CELL(0.114 ns) 2.389 ns numb\[4\]~1390 5 COMB LC_X6_Y17_N1 4 " "Info: 5: + IC(0.458 ns) + CELL(0.114 ns) = 2.389 ns; Loc. = LC_X6_Y17_N1; Fanout = 4; COMB Node = 'numb\[4\]~1390'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.572 ns" { numb[0]~1384 numb[4]~1390 } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.495 ns) + CELL(1.225 ns) 4.109 ns numb\[4\] 6 REG LC_X6_Y17_N4 6 " "Info: 6: + IC(0.495 ns) + CELL(1.225 ns) = 4.109 ns; Loc. = LC_X6_Y17_N4; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.720 ns" { numb[4]~1390 numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.009 ns ( 48.89 % ) " "Info: Total cell delay = 2.009 ns ( 48.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns ( 51.11 % ) " "Info: Total interconnect delay = 2.100 ns ( 51.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.109 ns" { numb[4] Equal2~93 Equal2~94 numb[0]~1384 numb[4]~1390 numb[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.109 ns" { numb[4] {} Equal2~93 {} Equal2~94 {} numb[0]~1384 {} numb[4]~1390 {} numb[4] {} } { 0.000ns 0.536ns 0.429ns 0.182ns 0.458ns 0.495ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.114ns 1.225ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns numb\[4\] 2 REG LC_X6_Y17_N4 6 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y17_N4; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK numb[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[4] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns numb\[4\] 2 REG LC_X6_Y17_N4 6 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y17_N4; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK numb[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[4] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK numb[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[4] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[4] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.109 ns" { numb[4] Equal2~93 Equal2~94 numb[0]~1384 numb[4]~1390 numb[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.109 ns" { numb[4] {} Equal2~93 {} Equal2~94 {} numb[0]~1384 {} numb[4]~1390 {} numb[4] {} } { 0.000ns 0.536ns 0.429ns 0.182ns 0.458ns 0.495ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.114ns 1.225ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK numb[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[4] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[4] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "LAMPB\[0\]~reg0 EN CLK 7.020 ns register " "Info: tsu for register \"LAMPB\[0\]~reg0\" (data pin = \"EN\", clock pin = \"CLK\") is 7.020 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.937 ns + Longest pin register " "Info: + Longest pin to register delay is 9.937 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns EN 1 PIN PIN_228 21 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_228; Fanout = 21; PIN Node = 'EN'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.034 ns) + CELL(0.292 ns) 7.801 ns LAMPB\[0\]~81 2 COMB LC_X9_Y14_N7 7 " "Info: 2: + IC(6.034 ns) + CELL(0.292 ns) = 7.801 ns; Loc. = LC_X9_Y14_N7; Fanout = 7; COMB Node = 'LAMPB\[0\]~81'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.326 ns" { EN LAMPB[0]~81 } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.269 ns) + CELL(0.867 ns) 9.937 ns LAMPB\[0\]~reg0 3 REG LC_X8_Y17_N9 3 " "Info: 3: + IC(1.269 ns) + CELL(0.867 ns) = 9.937 ns; Loc. = LC_X8_Y17_N9; Fanout = 3; REG Node = 'LAMPB\[0\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.136 ns" { LAMPB[0]~81 LAMPB[0]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.634 ns ( 26.51 % ) " "Info: Total cell delay = 2.634 ns ( 26.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.303 ns ( 73.49 % ) " "Info: Total interconnect delay = 7.303 ns ( 73.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.937 ns" { EN LAMPB[0]~81 LAMPB[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.937 ns" { EN {} EN~out0 {} LAMPB[0]~81 {} LAMPB[0]~reg0 {} } { 0.000ns 0.000ns 6.034ns 1.269ns } { 0.000ns 1.475ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns LAMPB\[0\]~reg0 2 REG LC_X8_Y17_N9 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X8_Y17_N9; Fanout = 3; REG Node = 'LAMPB\[0\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK LAMPB[0]~reg0 } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK LAMPB[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} LAMPB[0]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.937 ns" { EN LAMPB[0]~81 LAMPB[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.937 ns" { EN {} EN~out0 {} LAMPB[0]~81 {} LAMPB[0]~reg0 {} } { 0.000ns 0.000ns 6.034ns 1.269ns } { 0.000ns 1.475ns 0.292ns 0.867ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK LAMPB[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} LAMPB[0]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK BCOUNT\[4\] numb\[4\] 9.153 ns register " "Info: tco from clock \"CLK\" to destination pin \"BCOUNT\[4\]\" through register \"numb\[4\]\" is 9.153 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns numb\[4\] 2 REG LC_X6_Y17_N4 6 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y17_N4; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK numb[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[4] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.975 ns + Longest register pin " "Info: + Longest register to pin delay is 5.975 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numb\[4\] 1 REG LC_X6_Y17_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y17_N4; Fanout = 6; REG Node = 'numb\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { numb[4] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.851 ns) + CELL(2.124 ns) 5.975 ns BCOUNT\[4\] 2 PIN PIN_170 0 " "Info: 2: + IC(3.851 ns) + CELL(2.124 ns) = 5.975 ns; Loc. = PIN_170; Fanout = 0; PIN Node = 'BCOUNT\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.975 ns" { numb[4] BCOUNT[4] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 35.55 % ) " "Info: Total cell delay = 2.124 ns ( 35.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.851 ns ( 64.45 % ) " "Info: Total interconnect delay = 3.851 ns ( 64.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.975 ns" { numb[4] BCOUNT[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.975 ns" { numb[4] {} BCOUNT[4] {} } { 0.000ns 3.851ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK numb[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[4] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.975 ns" { numb[4] BCOUNT[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.975 ns" { numb[4] {} BCOUNT[4] {} } { 0.000ns 3.851ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "numb\[1\] EN CLK -4.117 ns register " "Info: th for register \"numb\[1\]\" (data pin = \"EN\", clock pin = \"CLK\") is -4.117 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 29; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns numb\[1\] 2 REG LC_X7_Y17_N1 8 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y17_N1; Fanout = 8; REG Node = 'numb\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK numb[1] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK numb[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.086 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns EN 1 PIN PIN_228 21 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_228; Fanout = 21; PIN Node = 'EN'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.133 ns) + CELL(0.478 ns) 7.086 ns numb\[1\] 2 REG LC_X7_Y17_N1 8 " "Info: 2: + IC(5.133 ns) + CELL(0.478 ns) = 7.086 ns; Loc. = LC_X7_Y17_N1; Fanout = 8; REG Node = 'numb\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.611 ns" { EN numb[1] } "NODE_NAME" } } { "traffic.v" "" { Text "C:/Users/123/Desktop/traffic/traffic.v" 76 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns ( 27.56 % ) " "Info: Total cell delay = 1.953 ns ( 27.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.133 ns ( 72.44 % ) " "Info: Total interconnect delay = 5.133 ns ( 72.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.086 ns" { EN numb[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.086 ns" { EN {} EN~out0 {} numb[1] {} } { 0.000ns 0.000ns 5.133ns } { 0.000ns 1.475ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK numb[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} numb[1] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.086 ns" { EN numb[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.086 ns" { EN {} EN~out0 {} numb[1] {} } { 0.000ns 0.000ns 5.133ns } { 0.000ns 1.475ns 0.478ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}