traffic.tan.summary

来自「verilog HDl 交通灯的实现,而且这是有别于一般的vhdl语言」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.020 ns
From           : EN
To             : LAMPB[3]~reg0
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.153 ns
From           : numb[4]
To             : BCOUNT[4]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.117 ns
From           : EN
To             : numb[1]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 228.83 MHz ( period = 4.370 ns )
From           : numb[4]
To             : numb[6]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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