📄 lcd_ocmj2_8.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_ocmj2_8 is
Port ( clk : in std_logic;
reset:in std_logic;
lcd_en : out std_logic;
lcd_data : out std_logic_vector(7 downto 0));
end lcd_ocmj2_8;
architecture Behavioral of lcd_ocmj2_8 is
type state is (set_dlnf,set_order,set_x,set_y,write_qu,write_wei);
signal current_state:state;
begin
lcd_en <= clk ;
--current_state<=set_order;
process
begin
if(reset = '0')then
current_state<=set_dlnf;
elsif(rising_edge(clk))then
current_state <= current_state;
case current_state is
when set_dlnf=>
lcd_data<="11110100";
current_state<=set_order;
when set_order=>
lcd_data<="11110000";
current_state<=set_x;
when set_x=>
lcd_data<="00000000";
current_state<=set_y;
when set_y=>
lcd_data<="00000000";
current_state<=write_qu;
when write_qu=>
lcd_data<="00010000";
current_state<=write_wei;
when write_wei=>
lcd_data<="00000001";
when others => null;
end case;
END IF;
-- write("11110100","11110000","00000111","00000001","00010011","00111101");
--write("11110100","11110000","00000001","00000000","00010000","00000001");
end process;
end Behavioral;
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