📄 lcd_ocmj2_8.rpt
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Device-Specific Information: f:\eda\lcd_ocmj2_8.rpt
lcd_ocmj2_8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - E 01 DFFE 2 1 0 2 current_state~2
- 4 - E 01 DFFE 2 1 0 3 current_state~3
- 3 - E 01 DFFE 2 1 0 3 current_state~4
- 8 - E 01 DFFE 2 1 0 6 current_state~5
- 1 - E 01 DFFE 2 0 0 7 current_state~6
- 1 - E 05 LCELL s 1 0 1 0 lcd_en~1
- 4 - E 10 DFFE 2 2 1 0 :4
- 1 - E 08 DFFE 2 2 1 0 :6
- 4 - E 08 DFFE 2 2 1 0 :8
- 4 - E 05 DFFE 2 3 1 0 :10
- 4 - E 03 DFFE 2 1 1 0 :14
- 6 - E 01 DFFE 2 3 1 0 :18
- 2 - E 01 AND2 0 3 0 1 :255
- 7 - E 01 AND2 s 0 3 0 1 ~330~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\eda\lcd_ocmj2_8.rpt
lcd_ocmj2_8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 4/144( 2%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda\lcd_ocmj2_8.rpt
lcd_ocmj2_8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
Device-Specific Information: f:\eda\lcd_ocmj2_8.rpt
lcd_ocmj2_8
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 11 reset
Device-Specific Information: f:\eda\lcd_ocmj2_8.rpt
lcd_ocmj2_8
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is 'current_state~2'
-- Equation name is 'current_state~2', location is LC5_E1, type is buried.
current_state~2 = DFFE( current_state~3, clk, reset, VCC, VCC);
-- Node name is 'current_state~3'
-- Equation name is 'current_state~3', location is LC4_E1, type is buried.
current_state~3 = DFFE( current_state~4, clk, reset, VCC, VCC);
-- Node name is 'current_state~4'
-- Equation name is 'current_state~4', location is LC3_E1, type is buried.
current_state~4 = DFFE( current_state~5, clk, reset, VCC, VCC);
-- Node name is 'current_state~5'
-- Equation name is 'current_state~5', location is LC8_E1, type is buried.
current_state~5 = DFFE(!current_state~6, clk, reset, VCC, VCC);
-- Node name is 'current_state~6'
-- Equation name is 'current_state~6', location is LC1_E1, type is buried.
current_state~6 = DFFE( VCC, clk, reset, VCC, VCC);
-- Node name is 'lcd_data0'
-- Equation name is 'lcd_data0', type is output
lcd_data0 = _LC6_E1;
-- Node name is 'lcd_data1'
-- Equation name is 'lcd_data1', type is output
lcd_data1 = GND;
-- Node name is 'lcd_data2'
-- Equation name is 'lcd_data2', type is output
lcd_data2 = _LC4_E3;
-- Node name is 'lcd_data3'
-- Equation name is 'lcd_data3', type is output
lcd_data3 = GND;
-- Node name is 'lcd_data4'
-- Equation name is 'lcd_data4', type is output
lcd_data4 = _LC4_E5;
-- Node name is 'lcd_data5'
-- Equation name is 'lcd_data5', type is output
lcd_data5 = _LC4_E8;
-- Node name is 'lcd_data6'
-- Equation name is 'lcd_data6', type is output
lcd_data6 = _LC1_E8;
-- Node name is 'lcd_data7'
-- Equation name is 'lcd_data7', type is output
lcd_data7 = _LC4_E10;
-- Node name is 'lcd_en'
-- Equation name is 'lcd_en', type is output
lcd_en = _LC1_E5;
-- Node name is 'lcd_en~1'
-- Equation name is 'lcd_en~1', location is LC1_E5, type is buried.
-- synthesized logic cell
_LC1_E5 = LCELL( clk);
-- Node name is ':4'
-- Equation name is '_LC4_E10', type is buried
_LC4_E10 = DFFE( _EQ001, clk, VCC, VCC, reset);
_EQ001 = current_state~5
# !current_state~6;
-- Node name is ':6'
-- Equation name is '_LC1_E8', type is buried
_LC1_E8 = DFFE( _EQ002, clk, VCC, VCC, reset);
_EQ002 = current_state~5
# !current_state~6;
-- Node name is ':8'
-- Equation name is '_LC4_E8', type is buried
_LC4_E8 = DFFE( _EQ003, clk, VCC, VCC, reset);
_EQ003 = current_state~5
# !current_state~6;
-- Node name is ':10'
-- Equation name is '_LC4_E5', type is buried
_LC4_E5 = DFFE( _EQ004, clk, VCC, VCC, reset);
_EQ004 = current_state~5
# !current_state~6
# _LC2_E1;
-- Node name is ':14'
-- Equation name is '_LC4_E3', type is buried
_LC4_E3 = DFFE(!current_state~6, clk, VCC, VCC, reset);
-- Node name is ':18'
-- Equation name is '_LC6_E1', type is buried
_LC6_E1 = DFFE( _EQ005, clk, VCC, VCC, reset);
_EQ005 = !current_state~5 & current_state~6 & _LC7_E1;
-- Node name is ':255'
-- Equation name is '_LC2_E1', type is buried
_LC2_E1 = LCELL( _EQ006);
_EQ006 = current_state~2 & !current_state~3 & !current_state~4;
-- Node name is '~330~1'
-- Equation name is '~330~1', location is LC7_E1, type is buried.
-- synthesized logic cell
_LC7_E1 = LCELL( _EQ007);
_EQ007 = !current_state~2 & !current_state~3 & !current_state~4;
Project Information f:\eda\lcd_ocmj2_8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 31,504K
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