📄 and-2.tan.rpt
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Timing Analyzer report for and-2
Tue Apr 07 20:02:52 2009
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-----------+------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-----------+------------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 19.203 ns ; pin_name3 ; pin_name32 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-----------+------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------------+------------+
; N/A ; None ; 19.203 ns ; pin_name3 ; pin_name32 ;
; N/A ; None ; 18.550 ns ; pin_name ; pin_name32 ;
; N/A ; None ; 18.487 ns ; pin_name3 ; pin_name29 ;
; N/A ; None ; 18.417 ns ; pin_name4 ; pin_name32 ;
; N/A ; None ; 17.998 ns ; pin_name3 ; pin_name31 ;
; N/A ; None ; 17.981 ns ; pin_name8 ; pin_name32 ;
; N/A ; None ; 17.960 ns ; pin_name3 ; pin_name30 ;
; N/A ; None ; 17.834 ns ; pin_name ; pin_name29 ;
; N/A ; None ; 17.772 ns ; pin_name3 ; pin_name35 ;
; N/A ; None ; 17.706 ns ; pin_name5 ; pin_name32 ;
; N/A ; None ; 17.701 ns ; pin_name4 ; pin_name29 ;
; N/A ; None ; 17.676 ns ; pin_name19 ; pin_name32 ;
; N/A ; None ; 17.516 ns ; pin_name20 ; pin_name32 ;
; N/A ; None ; 17.345 ns ; pin_name ; pin_name31 ;
; N/A ; None ; 17.307 ns ; pin_name ; pin_name30 ;
; N/A ; None ; 17.288 ns ; pin_name22 ; pin_name32 ;
; N/A ; None ; 17.273 ns ; pin_name21 ; pin_name32 ;
; N/A ; None ; 17.265 ns ; pin_name8 ; pin_name29 ;
; N/A ; None ; 17.250 ns ; pin_name18 ; pin_name32 ;
; N/A ; None ; 17.212 ns ; pin_name4 ; pin_name31 ;
; N/A ; None ; 17.174 ns ; pin_name4 ; pin_name30 ;
; N/A ; None ; 17.119 ns ; pin_name ; pin_name35 ;
; N/A ; None ; 17.057 ns ; pin_name6 ; pin_name32 ;
; N/A ; None ; 17.029 ns ; pin_name7 ; pin_name32 ;
; N/A ; None ; 16.990 ns ; pin_name5 ; pin_name29 ;
; N/A ; None ; 16.986 ns ; pin_name4 ; pin_name35 ;
; N/A ; None ; 16.960 ns ; pin_name19 ; pin_name29 ;
; N/A ; None ; 16.882 ns ; pin_name3 ; pin_name28 ;
; N/A ; None ; 16.800 ns ; pin_name20 ; pin_name29 ;
; N/A ; None ; 16.776 ns ; pin_name8 ; pin_name31 ;
; N/A ; None ; 16.743 ns ; pin_name3 ; pin_name33 ;
; N/A ; None ; 16.738 ns ; pin_name8 ; pin_name30 ;
; N/A ; None ; 16.572 ns ; pin_name22 ; pin_name29 ;
; N/A ; None ; 16.557 ns ; pin_name21 ; pin_name29 ;
; N/A ; None ; 16.550 ns ; pin_name8 ; pin_name35 ;
; N/A ; None ; 16.534 ns ; pin_name18 ; pin_name29 ;
; N/A ; None ; 16.501 ns ; pin_name5 ; pin_name31 ;
; N/A ; None ; 16.471 ns ; pin_name19 ; pin_name31 ;
; N/A ; None ; 16.463 ns ; pin_name5 ; pin_name30 ;
; N/A ; None ; 16.433 ns ; pin_name19 ; pin_name30 ;
; N/A ; None ; 16.341 ns ; pin_name6 ; pin_name29 ;
; N/A ; None ; 16.313 ns ; pin_name7 ; pin_name29 ;
; N/A ; None ; 16.311 ns ; pin_name20 ; pin_name31 ;
; N/A ; None ; 16.275 ns ; pin_name5 ; pin_name35 ;
; N/A ; None ; 16.273 ns ; pin_name20 ; pin_name30 ;
; N/A ; None ; 16.245 ns ; pin_name19 ; pin_name35 ;
; N/A ; None ; 16.239 ns ; pin_name3 ; pin_name34 ;
; N/A ; None ; 16.229 ns ; pin_name ; pin_name28 ;
; N/A ; None ; 16.096 ns ; pin_name4 ; pin_name28 ;
; N/A ; None ; 16.090 ns ; pin_name ; pin_name33 ;
; N/A ; None ; 16.085 ns ; pin_name20 ; pin_name35 ;
; N/A ; None ; 16.083 ns ; pin_name22 ; pin_name31 ;
; N/A ; None ; 16.068 ns ; pin_name21 ; pin_name31 ;
; N/A ; None ; 16.045 ns ; pin_name18 ; pin_name31 ;
; N/A ; None ; 16.045 ns ; pin_name22 ; pin_name30 ;
; N/A ; None ; 16.030 ns ; pin_name21 ; pin_name30 ;
; N/A ; None ; 16.007 ns ; pin_name18 ; pin_name30 ;
; N/A ; None ; 15.857 ns ; pin_name22 ; pin_name35 ;
; N/A ; None ; 15.852 ns ; pin_name6 ; pin_name31 ;
; N/A ; None ; 15.842 ns ; pin_name21 ; pin_name35 ;
; N/A ; None ; 15.829 ns ; pin_name4 ; pin_name33 ;
; N/A ; None ; 15.824 ns ; pin_name7 ; pin_name31 ;
; N/A ; None ; 15.819 ns ; pin_name18 ; pin_name35 ;
; N/A ; None ; 15.814 ns ; pin_name6 ; pin_name30 ;
; N/A ; None ; 15.786 ns ; pin_name7 ; pin_name30 ;
; N/A ; None ; 15.660 ns ; pin_name8 ; pin_name28 ;
; N/A ; None ; 15.626 ns ; pin_name6 ; pin_name35 ;
; N/A ; None ; 15.598 ns ; pin_name7 ; pin_name35 ;
; N/A ; None ; 15.586 ns ; pin_name ; pin_name34 ;
; N/A ; None ; 15.523 ns ; pin_name19 ; pin_name33 ;
; N/A ; None ; 15.453 ns ; pin_name4 ; pin_name34 ;
; N/A ; None ; 15.385 ns ; pin_name5 ; pin_name28 ;
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