📄 and-2.tan.rpt
字号:
Timing Analyzer report for and-2
Tue Apr 07 19:24:16 2009
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 16.681 ns ; pin_name11 ; pin_name20 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------------+------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------------+------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------------+------------+
; N/A ; None ; 16.681 ns ; pin_name11 ; pin_name20 ;
; N/A ; None ; 15.743 ns ; pin_name11 ; pin_name21 ;
; N/A ; None ; 15.654 ns ; pin_name11 ; pin_name19 ;
; N/A ; None ; 15.544 ns ; pin_name11 ; pin_name18 ;
; N/A ; None ; 15.473 ns ; pin_name10 ; pin_name20 ;
; N/A ; None ; 15.432 ns ; pin_name ; pin_name20 ;
; N/A ; None ; 14.992 ns ; pin_name12 ; pin_name20 ;
; N/A ; None ; 14.913 ns ; pin_name3 ; pin_name20 ;
; N/A ; None ; 14.903 ns ; pin_name13 ; pin_name20 ;
; N/A ; None ; 14.648 ns ; pin_name11 ; pin_name17 ;
; N/A ; None ; 14.575 ns ; pin_name2 ; pin_name20 ;
; N/A ; None ; 14.535 ns ; pin_name10 ; pin_name21 ;
; N/A ; None ; 14.494 ns ; pin_name ; pin_name21 ;
; N/A ; None ; 14.446 ns ; pin_name10 ; pin_name19 ;
; N/A ; None ; 14.405 ns ; pin_name1 ; pin_name20 ;
; N/A ; None ; 14.405 ns ; pin_name ; pin_name19 ;
; N/A ; None ; 14.380 ns ; pin_name11 ; pin_name14 ;
; N/A ; None ; 14.336 ns ; pin_name10 ; pin_name18 ;
; N/A ; None ; 14.295 ns ; pin_name ; pin_name18 ;
; N/A ; None ; 14.154 ns ; pin_name4 ; pin_name20 ;
; N/A ; None ; 14.054 ns ; pin_name12 ; pin_name21 ;
; N/A ; None ; 13.984 ns ; pin_name4 ; pin_name21 ;
; N/A ; None ; 13.975 ns ; pin_name3 ; pin_name21 ;
; N/A ; None ; 13.965 ns ; pin_name13 ; pin_name21 ;
; N/A ; None ; 13.965 ns ; pin_name12 ; pin_name19 ;
; N/A ; None ; 13.886 ns ; pin_name3 ; pin_name19 ;
; N/A ; None ; 13.876 ns ; pin_name13 ; pin_name19 ;
; N/A ; None ; 13.855 ns ; pin_name12 ; pin_name18 ;
; N/A ; None ; 13.847 ns ; pin_name6 ; pin_name21 ;
; N/A ; None ; 13.787 ns ; pin_name11 ; pin_name16 ;
; N/A ; None ; 13.776 ns ; pin_name3 ; pin_name18 ;
; N/A ; None ; 13.766 ns ; pin_name13 ; pin_name18 ;
; N/A ; None ; 13.724 ns ; pin_name6 ; pin_name20 ;
; N/A ; None ; 13.674 ns ; pin_name5 ; pin_name20 ;
; N/A ; None ; 13.637 ns ; pin_name2 ; pin_name21 ;
; N/A ; None ; 13.548 ns ; pin_name2 ; pin_name19 ;
; N/A ; None ; 13.504 ns ; pin_name5 ; pin_name21 ;
; N/A ; None ; 13.503 ns ; pin_name7 ; pin_name20 ;
; N/A ; None ; 13.469 ns ; pin_name9 ; pin_name20 ;
; N/A ; None ; 13.467 ns ; pin_name1 ; pin_name21 ;
; N/A ; None ; 13.440 ns ; pin_name10 ; pin_name17 ;
; N/A ; None ; 13.438 ns ; pin_name2 ; pin_name18 ;
; N/A ; None ; 13.399 ns ; pin_name ; pin_name17 ;
; N/A ; None ; 13.378 ns ; pin_name1 ; pin_name19 ;
; N/A ; None ; 13.314 ns ; pin_name7 ; pin_name21 ;
; N/A ; None ; 13.268 ns ; pin_name1 ; pin_name18 ;
; N/A ; None ; 13.215 ns ; pin_name8 ; pin_name20 ;
; N/A ; None ; 13.172 ns ; pin_name10 ; pin_name14 ;
; N/A ; None ; 13.131 ns ; pin_name ; pin_name14 ;
; N/A ; None ; 13.127 ns ; pin_name4 ; pin_name19 ;
; N/A ; None ; 12.999 ns ; pin_name12 ; pin_name17 ;
; N/A ; None ; 12.910 ns ; pin_name13 ; pin_name17 ;
; N/A ; None ; 12.697 ns ; pin_name6 ; pin_name19 ;
; N/A ; None ; 12.691 ns ; pin_name12 ; pin_name14 ;
; N/A ; None ; 12.647 ns ; pin_name5 ; pin_name19 ;
; N/A ; None ; 12.612 ns ; pin_name3 ; pin_name14 ;
; N/A ; None ; 12.602 ns ; pin_name13 ; pin_name14 ;
; N/A ; None ; 12.589 ns ; pin_name4 ; pin_name18 ;
; N/A ; None ; 12.579 ns ; pin_name10 ; pin_name16 ;
; N/A ; None ; 12.538 ns ; pin_name ; pin_name16 ;
; N/A ; None ; 12.476 ns ; pin_name7 ; pin_name19 ;
; N/A ; None ; 12.388 ns ; pin_name4 ; pin_name14 ;
; N/A ; None ; 12.372 ns ; pin_name1 ; pin_name17 ;
; N/A ; None ; 12.314 ns ; pin_name6 ; pin_name14 ;
; N/A ; None ; 12.274 ns ; pin_name2 ; pin_name14 ;
; N/A ; None ; 12.147 ns ; pin_name4 ; pin_name15 ;
; N/A ; None ; 12.135 ns ; pin_name12 ; pin_name16 ;
; N/A ; None ; 12.132 ns ; pin_name12 ; pin_name15 ;
; N/A ; None ; 12.109 ns ; pin_name5 ; pin_name18 ;
; N/A ; None ; 12.104 ns ; pin_name1 ; pin_name14 ;
; N/A ; None ; 12.053 ns ; pin_name3 ; pin_name15 ;
; N/A ; None ; 12.046 ns ; pin_name13 ; pin_name16 ;
; N/A ; None ; 12.043 ns ; pin_name13 ; pin_name15 ;
; N/A ; None ; 12.010 ns ; pin_name6 ; pin_name15 ;
; N/A ; None ; 11.923 ns ; pin_name5 ; pin_name14 ;
; N/A ; None ; 11.846 ns ; pin_name7 ; pin_name14 ;
; N/A ; None ; 11.845 ns ; pin_name ; pin_name15 ;
; N/A ; None ; 11.718 ns ; pin_name9 ; pin_name17 ;
; N/A ; None ; 11.715 ns ; pin_name2 ; pin_name15 ;
; N/A ; None ; 11.667 ns ; pin_name5 ; pin_name15 ;
; N/A ; None ; 11.511 ns ; pin_name1 ; pin_name16 ;
; N/A ; None ; 11.477 ns ; pin_name7 ; pin_name15 ;
; N/A ; None ; 11.464 ns ; pin_name8 ; pin_name17 ;
; N/A ; None ; 11.441 ns ; pin_name8 ; pin_name19 ;
; N/A ; None ; 11.399 ns ; pin_name9 ; pin_name19 ;
; N/A ; None ; 11.331 ns ; pin_name8 ; pin_name18 ;
; N/A ; None ; 11.087 ns ; pin_name8 ; pin_name21 ;
; N/A ; None ; 11.072 ns ; pin_name3 ; pin_name17 ;
; N/A ; None ; 10.859 ns ; pin_name9 ; pin_name16 ;
; N/A ; None ; 10.858 ns ; pin_name9 ; pin_name18 ;
; N/A ; None ; 10.822 ns ; pin_name1 ; pin_name15 ;
; N/A ; None ; 10.731 ns ; pin_name2 ; pin_name17 ;
; N/A ; None ; 10.605 ns ; pin_name8 ; pin_name16 ;
+-------+-------------------+-----------------+------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Tue Apr 07 19:24:16 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off and-2 -c and-2 --timing_analysis_only
Info: Longest tpd from source pin "pin_name11" to destination pin "pin_name20" is 16.681 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_238; Fanout = 4; PIN Node = 'pin_name11'
Info: 2: + IC(6.570 ns) + CELL(0.442 ns) = 8.487 ns; Loc. = LC_X1_Y4_N6; Fanout = 3; COMB Node = '74181:inst|43~23'
Info: 3: + IC(0.434 ns) + CELL(0.590 ns) = 9.511 ns; Loc. = LC_X1_Y4_N8; Fanout = 2; COMB Node = '74181:inst|75~306'
Info: 4: + IC(1.206 ns) + CELL(0.442 ns) = 11.159 ns; Loc. = LC_X1_Y5_N2; Fanout = 2; COMB Node = '74181:inst|75~307'
Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 11.455 ns; Loc. = LC_X1_Y5_N3; Fanout = 1; COMB Node = '74181:inst|74~40'
Info: 6: + IC(0.425 ns) + CELL(0.114 ns) = 11.994 ns; Loc. = LC_X1_Y5_N6; Fanout = 2; COMB Node = '74181:inst|77'
Info: 7: + IC(0.441 ns) + CELL(0.590 ns) = 13.025 ns; Loc. = LC_X1_Y5_N5; Fanout = 1; COMB Node = '74181:inst|83'
Info: 8: + IC(1.532 ns) + CELL(2.124 ns) = 16.681 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'pin_name20'
Info: Total cell delay = 5.891 ns ( 35.32 % )
Info: Total interconnect delay = 10.790 ns ( 64.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Apr 07 19:24:16 2009
Info: Elapsed time: 00:00:01
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