📄 add.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 4/ 48( 8%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\max2work\dac0832\add.rpt
add
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\max2work\dac0832\add.rpt
add
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
-- Node name is 'add0'
-- Equation name is 'add0', type is output
add0 = tmp0;
-- Node name is 'add1'
-- Equation name is 'add1', type is output
add1 = tmp1;
-- Node name is 'add2'
-- Equation name is 'add2', type is output
add2 = tmp2;
-- Node name is 'add3'
-- Equation name is 'add3', type is output
add3 = tmp3;
-- Node name is 'add4'
-- Equation name is 'add4', type is output
add4 = tmp4;
-- Node name is 'add5'
-- Equation name is 'add5', type is output
add5 = tmp5;
-- Node name is 'add6'
-- Equation name is 'add6', type is output
add6 = tmp6;
-- Node name is 'add7'
-- Equation name is 'add7', type is output
add7 = tmp7;
-- Node name is ':18' = 'tmp0'
-- Equation name is 'tmp0', location is LC2_A18, type is buried.
tmp0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = clk1 & !tmp0
# !clk1 & tmp0;
-- Node name is ':17' = 'tmp1'
-- Equation name is 'tmp1', location is LC4_A18, type is buried.
tmp1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !clk1 & !tmp1
# clk1 & !tmp0 & tmp1
# tmp0 & !tmp1;
-- Node name is ':16' = 'tmp2'
-- Equation name is 'tmp2', location is LC7_A18, type is buried.
tmp2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !clk1 & tmp1 & !tmp2
# !tmp1 & tmp2
# clk1 & !tmp0 & tmp2
# tmp0 & tmp1 & !tmp2;
-- Node name is ':15' = 'tmp3'
-- Equation name is 'tmp3', location is LC1_A18, type is buried.
tmp3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !clk1 & !_LC3_A18 & tmp3
# !clk1 & _LC3_A18 & !tmp3
# clk1 & !_LC5_A18 & tmp3
# clk1 & _LC5_A18 & !tmp3;
-- Node name is ':14' = 'tmp4'
-- Equation name is 'tmp4', location is LC6_A6, type is buried.
tmp4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = clk1 & !_LC8_A18 & tmp4
# clk1 & _LC8_A18 & !tmp4
# !clk1 & !_LC6_A18 & tmp4
# !clk1 & _LC6_A18 & !tmp4;
-- Node name is ':13' = 'tmp5'
-- Equation name is 'tmp5', location is LC5_A6, type is buried.
tmp5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = clk1 & !_LC3_A6 & tmp5
# clk1 & _LC3_A6 & !tmp5
# !clk1 & !_LC4_A6 & tmp5
# !clk1 & _LC4_A6 & !tmp5;
-- Node name is ':12' = 'tmp6'
-- Equation name is 'tmp6', location is LC2_A6, type is buried.
tmp6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !clk1 & !_LC7_A6 & tmp6
# !clk1 & _LC7_A6 & !tmp6
# clk1 & !_LC8_A6 & tmp6
# clk1 & _LC8_A6 & !tmp6;
-- Node name is ':11' = 'tmp7'
-- Equation name is 'tmp7', location is LC1_A5, type is buried.
tmp7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !clk1 & !_LC1_A6 & tmp7
# !clk1 & _LC1_A6 & !tmp7
# clk1 & !_LC2_A5 & tmp7
# clk1 & _LC2_A5 & !tmp7;
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = LCELL( _EQ009);
_EQ009 = tmp1 & tmp2;
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A18', type is buried
_LC6_A18 = LCELL( _EQ010);
_EQ010 = tmp1 & tmp2 & tmp3;
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ011);
_EQ011 = _LC6_A18 & tmp4;
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = LCELL( _EQ012);
_EQ012 = _LC6_A18 & tmp4 & tmp5;
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ013);
_EQ013 = _LC6_A18 & tmp4 & tmp5 & tmp6;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ014);
_EQ014 = tmp0 & tmp1 & tmp2;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = LCELL( _EQ015);
_EQ015 = tmp0 & tmp1 & tmp2 & tmp3;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A6', type is buried
_LC3_A6 = LCELL( _EQ016);
_EQ016 = _LC8_A18 & tmp4;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = LCELL( _EQ017);
_EQ017 = _LC8_A18 & tmp4 & tmp5;
-- Node name is '|LPM_ADD_SUB:102|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ018);
_EQ018 = _LC8_A18 & tmp4 & tmp5 & tmp6;
Project Information d:\max2work\dac0832\add.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,450K
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