📄 triangle.rpt
字号:
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 21 AND2 0 3 0 3 |LPM_ADD_SUB:42|addcore:adder|:125
- 8 - C 21 AND2 0 3 0 3 |LPM_ADD_SUB:42|addcore:adder|:133
- 2 - C 21 DFFE 1 3 1 0 tmp7 (:10)
- 7 - C 21 DFFE 1 2 1 1 tmp6 (:11)
- 5 - C 21 DFFE 1 1 1 2 tmp5 (:12)
- 4 - C 21 DFFE 1 2 1 1 tmp4 (:13)
- 3 - C 21 DFFE 1 1 1 2 tmp3 (:14)
- 1 - C 21 DFFE 1 2 1 1 tmp2 (:15)
- 7 - A 19 DFFE 1 1 1 2 tmp1 (:16)
- 5 - A 19 DFFE 1 0 1 3 tmp0 (:17)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\max2work\dac0832\triangle.rpt
triangle
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 8/ 48( 16%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\max2work\dac0832\triangle.rpt
triangle
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\max2work\dac0832\triangle.rpt
triangle
** EQUATIONS **
clk : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = tmp0;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = tmp1;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = tmp2;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = tmp3;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = tmp4;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = tmp5;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = tmp6;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = tmp7;
-- Node name is ':17' = 'tmp0'
-- Equation name is 'tmp0', location is LC5_A19, type is buried.
tmp0 = DFFE(!tmp0, clk, VCC, VCC, VCC);
-- Node name is ':16' = 'tmp1'
-- Equation name is 'tmp1', location is LC7_A19, type is buried.
tmp1 = DFFE( _EQ001, clk, VCC, VCC, VCC);
_EQ001 = !tmp0 & tmp1
# tmp0 & !tmp1;
-- Node name is ':15' = 'tmp2'
-- Equation name is 'tmp2', location is LC1_C21, type is buried.
tmp2 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = !tmp1 & tmp2
# !tmp0 & tmp2
# tmp0 & tmp1 & !tmp2;
-- Node name is ':14' = 'tmp3'
-- Equation name is 'tmp3', location is LC3_C21, type is buried.
tmp3 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = !_LC6_C21 & tmp3
# _LC6_C21 & !tmp3;
-- Node name is ':13' = 'tmp4'
-- Equation name is 'tmp4', location is LC4_C21, type is buried.
tmp4 = DFFE( _EQ004, clk, VCC, VCC, VCC);
_EQ004 = !tmp3 & tmp4
# !_LC6_C21 & tmp4
# _LC6_C21 & tmp3 & !tmp4;
-- Node name is ':12' = 'tmp5'
-- Equation name is 'tmp5', location is LC5_C21, type is buried.
tmp5 = DFFE( _EQ005, clk, VCC, VCC, VCC);
_EQ005 = !_LC8_C21 & tmp5
# _LC8_C21 & !tmp5;
-- Node name is ':11' = 'tmp6'
-- Equation name is 'tmp6', location is LC7_C21, type is buried.
tmp6 = DFFE( _EQ006, clk, VCC, VCC, VCC);
_EQ006 = !tmp5 & tmp6
# !_LC8_C21 & tmp6
# _LC8_C21 & tmp5 & !tmp6;
-- Node name is ':10' = 'tmp7'
-- Equation name is 'tmp7', location is LC2_C21, type is buried.
tmp7 = DFFE( _EQ007, clk, VCC, VCC, VCC);
_EQ007 = !tmp5 & tmp7
# !_LC8_C21 & tmp7
# !tmp6 & tmp7
# _LC8_C21 & tmp5 & tmp6 & !tmp7;
-- Node name is '|LPM_ADD_SUB:42|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ008);
_EQ008 = tmp0 & tmp1 & tmp2;
-- Node name is '|LPM_ADD_SUB:42|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ009);
_EQ009 = _LC6_C21 & tmp3 & tmp4;
Project Information d:\max2work\dac0832\triangle.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,869K
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