📄 triangle1.rpt
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# !_LC7_C23 & tmp0 & tmp2
# !_LC7_C23 & !tmp0 & !tmp1 & !tmp2;
-- Node name is ':14' = 'tmp3'
-- Equation name is 'tmp3', location is LC3_C15, type is buried.
tmp3 = DFFE( _EQ010, clk, VCC, VCC, VCC);
_EQ010 = !_LC2_C15 & _LC7_C23 & tmp3
# _LC2_C15 & _LC7_C23 & !tmp3
# _LC6_C15 & !_LC7_C23 & tmp3
# !_LC6_C15 & !_LC7_C23 & !tmp3;
-- Node name is ':13' = 'tmp4'
-- Equation name is 'tmp4', location is LC4_C22, type is buried.
tmp4 = DFFE( _EQ011, clk, VCC, VCC, VCC);
_EQ011 = !_LC4_C15 & _LC7_C23 & tmp4
# _LC4_C15 & _LC7_C23 & !tmp4
# !_LC7_C23 & _LC8_C15 & tmp4
# !_LC7_C23 & !_LC8_C15 & !tmp4;
-- Node name is ':12' = 'tmp5'
-- Equation name is 'tmp5', location is LC5_C23, type is buried.
tmp5 = DFFE( _EQ012, clk, VCC, VCC, VCC);
_EQ012 = _LC5_C22 & !_LC7_C23 & tmp5
# !_LC5_C22 & !_LC7_C23 & !tmp5
# !_LC1_C16 & _LC7_C23 & tmp5
# _LC1_C16 & _LC7_C23 & !tmp5;
-- Node name is ':11' = 'tmp6'
-- Equation name is 'tmp6', location is LC6_C22, type is buried.
tmp6 = DFFE( _EQ013, clk, VCC, VCC, VCC);
_EQ013 = !_LC1_C22 & _LC7_C23 & tmp6
# _LC1_C22 & _LC7_C23 & !tmp6
# _LC2_C22 & !_LC7_C23 & tmp6
# !_LC2_C22 & !_LC7_C23 & !tmp6;
-- Node name is ':10' = 'tmp7'
-- Equation name is 'tmp7', location is LC3_C22, type is buried.
tmp7 = DFFE( _EQ014, clk, VCC, VCC, VCC);
_EQ014 = !_LC7_C22 & _LC7_C23 & tmp7
# _LC7_C22 & _LC7_C23 & !tmp7
# !_LC7_C23 & _LC8_C22 & tmp7
# !_LC7_C23 & !_LC8_C22 & !tmp7;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C19', type is buried
_LC5_C19 = LCELL( _EQ015);
_EQ015 = cnt0 & cnt1;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C19', type is buried
_LC8_C19 = LCELL( _EQ016);
_EQ016 = cnt0 & cnt1 & cnt2 & cnt3;
-- Node name is '|LPM_ADD_SUB:78|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ017);
_EQ017 = cnt4 & cnt5 & _LC8_C19;
-- Node name is '|LPM_ADD_SUB:202|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = LCELL( _EQ018);
_EQ018 = tmp0 & tmp1 & tmp2;
-- Node name is '|LPM_ADD_SUB:202|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C15', type is buried
_LC4_C15 = LCELL( _EQ019);
_EQ019 = tmp0 & tmp1 & tmp2 & tmp3;
-- Node name is '|LPM_ADD_SUB:202|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = LCELL( _EQ020);
_EQ020 = _LC4_C15 & tmp4;
-- Node name is '|LPM_ADD_SUB:202|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = LCELL( _EQ021);
_EQ021 = _LC4_C15 & tmp4 & tmp5;
-- Node name is '|LPM_ADD_SUB:202|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C22', type is buried
_LC7_C22 = LCELL( _EQ022);
_EQ022 = _LC4_C15 & tmp4 & tmp5 & tmp6;
-- Node name is '|LPM_ADD_SUB:243|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C15', type is buried
_LC6_C15 = LCELL( _EQ023);
_EQ023 = tmp1
# tmp0
# tmp2;
-- Node name is '|LPM_ADD_SUB:243|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C15', type is buried
_LC8_C15 = LCELL( _EQ024);
_EQ024 = tmp1
# tmp0
# tmp2
# tmp3;
-- Node name is '|LPM_ADD_SUB:243|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ025);
_EQ025 = tmp4
# _LC8_C15;
-- Node name is '|LPM_ADD_SUB:243|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = LCELL( _EQ026);
_EQ026 = tmp4
# _LC8_C15
# tmp5;
-- Node name is '|LPM_ADD_SUB:243|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C22', type is buried
_LC8_C22 = LCELL( _EQ027);
_EQ027 = tmp4
# _LC8_C15
# tmp5
# tmp6;
-- Node name is '~52~1'
-- Equation name is '~52~1', location is LC3_C19, type is buried.
-- synthesized logic cell
_LC3_C19 = LCELL( _EQ028);
_EQ028 = cnt1
# cnt3
# cnt2;
-- Node name is '~52~2'
-- Equation name is '~52~2', location is LC1_C19, type is buried.
-- synthesized logic cell
_LC1_C19 = LCELL( _EQ029);
_EQ029 = cnt0
# cnt5
# cnt6;
-- Node name is ':52'
-- Equation name is '_LC8_C23', type is buried
!_LC8_C23 = _LC8_C23~NOT;
_LC8_C23~NOT = LCELL( _EQ030);
_EQ030 = !cnt7
# cnt4
# _LC3_C19
# _LC1_C19;
-- Node name is ':143'
-- Equation name is '_LC7_C23', type is buried
!_LC7_C23 = _LC7_C23~NOT;
_LC7_C23~NOT = LCELL( _EQ031);
_EQ031 = cnt6 & !cnt7 & !_LC8_C23
# !cnt6 & cnt7 & !_LC8_C23
# cnt7 & !_LC2_C23 & !_LC8_C23
# cnt6 & !_LC2_C23 & !_LC8_C23;
Project Information d:\max2work\dac0832\triangle1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,166K
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