📄 triangle1.rpt
字号:
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max2work\dac0832\triangle1.rpt
triangle1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
65 - - B -- OUTPUT 0 1 0 0 data0
64 - - B -- OUTPUT 0 1 0 0 data1
62 - - C -- OUTPUT 0 1 0 0 data2
61 - - C -- OUTPUT 0 1 0 0 data3
60 - - C -- OUTPUT 0 1 0 0 data4
59 - - C -- OUTPUT 0 1 0 0 data5
58 - - C -- OUTPUT 0 1 0 0 data6
54 - - - 21 OUTPUT 0 1 0 0 data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max2work\dac0832\triangle1.rpt
triangle1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 19 AND2 0 2 0 1 |LPM_ADD_SUB:78|addcore:adder|:75
- 8 - C 19 AND2 0 4 0 3 |LPM_ADD_SUB:78|addcore:adder|:83
- 2 - C 23 AND2 0 3 0 3 |LPM_ADD_SUB:78|addcore:adder|:91
- 2 - C 15 AND2 0 3 0 1 |LPM_ADD_SUB:202|addcore:adder|:125
- 4 - C 15 AND2 0 4 0 4 |LPM_ADD_SUB:202|addcore:adder|:129
- 1 - C 16 AND2 0 2 0 1 |LPM_ADD_SUB:202|addcore:adder|:133
- 1 - C 22 AND2 0 3 0 1 |LPM_ADD_SUB:202|addcore:adder|:137
- 7 - C 22 AND2 0 4 0 1 |LPM_ADD_SUB:202|addcore:adder|:141
- 6 - C 15 OR2 0 3 0 1 |LPM_ADD_SUB:243|addcore:adder|pcarry2
- 8 - C 15 OR2 0 4 0 4 |LPM_ADD_SUB:243|addcore:adder|pcarry3
- 5 - C 22 OR2 0 2 0 1 |LPM_ADD_SUB:243|addcore:adder|pcarry4
- 2 - C 22 OR2 0 3 0 1 |LPM_ADD_SUB:243|addcore:adder|pcarry5
- 8 - C 22 OR2 0 4 0 1 |LPM_ADD_SUB:243|addcore:adder|pcarry6
- 3 - C 22 DFFE 1 3 1 0 tmp7 (:10)
- 6 - C 22 DFFE 1 3 1 2 tmp6 (:11)
- 5 - C 23 DFFE 1 3 1 4 tmp5 (:12)
- 4 - C 22 DFFE 1 3 1 6 tmp4 (:13)
- 3 - C 15 DFFE 1 3 1 2 tmp3 (:14)
- 1 - C 15 DFFE 1 3 1 4 tmp2 (:15)
- 7 - C 15 DFFE 1 2 1 5 tmp1 (:16)
- 5 - C 15 DFFE 1 0 1 6 tmp0 (:17)
- 4 - C 23 DFFE 1 3 0 2 cnt7 (:18)
- 6 - C 23 DFFE 1 2 0 3 cnt6 (:19)
- 3 - C 23 DFFE 1 3 0 2 cnt5 (:20)
- 1 - C 23 DFFE 1 2 0 3 cnt4 (:21)
- 6 - C 19 DFFE 1 3 0 2 cnt3 (:22)
- 2 - C 19 DFFE 1 3 0 3 cnt2 (:23)
- 4 - C 19 DFFE 1 2 0 4 cnt1 (:24)
- 7 - C 19 DFFE 1 0 0 5 cnt0 (:25)
- 3 - C 19 OR2 s 0 3 0 1 ~52~1
- 1 - C 19 OR2 s 0 3 0 1 ~52~2
- 8 - C 23 OR2 ! 0 4 0 8 :52
- 7 - C 23 OR2 ! 0 4 0 7 :143
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\max2work\dac0832\triangle1.rpt
triangle1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 18/ 48( 37%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\max2work\dac0832\triangle1.rpt
triangle1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: d:\max2work\dac0832\triangle1.rpt
triangle1
** EQUATIONS **
clk : INPUT;
-- Node name is ':25' = 'cnt0'
-- Equation name is 'cnt0', location is LC7_C19, type is buried.
cnt0 = DFFE(!cnt0, clk, VCC, VCC, VCC);
-- Node name is ':24' = 'cnt1'
-- Equation name is 'cnt1', location is LC4_C19, type is buried.
cnt1 = DFFE( _EQ001, clk, VCC, VCC, VCC);
_EQ001 = cnt0 & !cnt1 & !_LC8_C23
# !cnt0 & cnt1 & !_LC8_C23;
-- Node name is ':23' = 'cnt2'
-- Equation name is 'cnt2', location is LC2_C19, type is buried.
cnt2 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = !cnt0 & cnt2 & !_LC8_C23
# !cnt1 & cnt2 & !_LC8_C23
# cnt0 & cnt1 & !cnt2 & !_LC8_C23;
-- Node name is ':22' = 'cnt3'
-- Equation name is 'cnt3', location is LC6_C19, type is buried.
cnt3 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = cnt3 & !_LC5_C19 & !_LC8_C23
# !cnt2 & cnt3 & !_LC8_C23
# cnt2 & !cnt3 & _LC5_C19 & !_LC8_C23;
-- Node name is ':21' = 'cnt4'
-- Equation name is 'cnt4', location is LC1_C23, type is buried.
cnt4 = DFFE( _EQ004, clk, VCC, VCC, VCC);
_EQ004 = cnt4 & !_LC8_C19 & !_LC8_C23
# !cnt4 & _LC8_C19 & !_LC8_C23;
-- Node name is ':20' = 'cnt5'
-- Equation name is 'cnt5', location is LC3_C23, type is buried.
cnt5 = DFFE( _EQ005, clk, VCC, VCC, VCC);
_EQ005 = !cnt4 & cnt5 & !_LC8_C23
# cnt5 & !_LC8_C19 & !_LC8_C23
# cnt4 & !cnt5 & _LC8_C19 & !_LC8_C23;
-- Node name is ':19' = 'cnt6'
-- Equation name is 'cnt6', location is LC6_C23, type is buried.
cnt6 = DFFE( _EQ006, clk, VCC, VCC, VCC);
_EQ006 = cnt6 & !_LC2_C23 & !_LC8_C23
# !cnt6 & _LC2_C23 & !_LC8_C23;
-- Node name is ':18' = 'cnt7'
-- Equation name is 'cnt7', location is LC4_C23, type is buried.
cnt7 = DFFE( _EQ007, clk, VCC, VCC, VCC);
_EQ007 = !cnt6 & cnt7 & !_LC8_C23
# cnt7 & !_LC2_C23 & !_LC8_C23
# cnt6 & !cnt7 & _LC2_C23 & !_LC8_C23;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = tmp0;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = tmp1;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = tmp2;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = tmp3;
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = tmp4;
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = tmp5;
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = tmp6;
-- Node name is 'data7'
-- Equation name is 'data7', type is output
data7 = tmp7;
-- Node name is ':17' = 'tmp0'
-- Equation name is 'tmp0', location is LC5_C15, type is buried.
tmp0 = DFFE(!tmp0, clk, VCC, VCC, VCC);
-- Node name is ':16' = 'tmp1'
-- Equation name is 'tmp1', location is LC7_C15, type is buried.
tmp1 = DFFE( _EQ008, clk, VCC, VCC, VCC);
_EQ008 = !_LC7_C23 & tmp0 & tmp1
# !_LC7_C23 & !tmp0 & !tmp1
# _LC7_C23 & !tmp0 & tmp1
# _LC7_C23 & tmp0 & !tmp1;
-- Node name is ':15' = 'tmp2'
-- Equation name is 'tmp2', location is LC1_C15, type is buried.
tmp2 = DFFE( _EQ009, clk, VCC, VCC, VCC);
_EQ009 = _LC7_C23 & !tmp1 & tmp2
# _LC7_C23 & !tmp0 & tmp2
# _LC7_C23 & tmp0 & tmp1 & !tmp2
# !_LC7_C23 & tmp1 & tmp2
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