sintop.rpt

关于CPLD程序

-- Equation name is 'data7~fit~in1', location is LC2_B21, type is buried.
-- synthesized logic cell 
_LC2_B21 = LCELL( _EC5_B);

-- Node name is 'data7' 
-- Equation name is 'data7', type is output 
data7    =  _LC2_B21;

-- Node name is '|ADD:1|LPM_ADD_SUB:61|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ001);
  _EQ001 =  _LC4_B5 &  _LC5_B5;

-- Node name is '|ADD:1|LPM_ADD_SUB:61|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ002);
  _EQ002 =  _LC3_B5 &  _LC4_B5 &  _LC5_B5;

-- Node name is '|ADD:1|LPM_ADD_SUB:61|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B8', type is buried 
_LC4_B8  = LCELL( _EQ003);
  _EQ003 =  _LC1_B5 &  _LC3_B5 &  _LC4_B5 &  _LC5_B5;

-- Node name is '|ADD:1|LPM_ADD_SUB:61|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B8', type is buried 
_LC5_B8  = LCELL( _EQ004);
  _EQ004 =  _LC1_B8 &  _LC4_B8;

-- Node name is '|ADD:1|LPM_ADD_SUB:61|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B8', type is buried 
_LC6_B8  = LCELL( _EQ005);
  _EQ005 =  _LC2_B8 &  _LC5_B8;

-- Node name is '|ADD:1|LPM_ADD_SUB:102|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = LCELL( _EQ006);
  _EQ006 =  _LC2_B10 &  _LC4_B5 &  _LC5_B5;

-- Node name is '|ADD:1|LPM_ADD_SUB:102|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ007);
  _EQ007 =  _LC2_B10 &  _LC3_B5 &  _LC4_B5 &  _LC5_B5;

-- Node name is '|ADD:1|LPM_ADD_SUB:102|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B9', type is buried 
_LC2_B9  = LCELL( _EQ008);
  _EQ008 =  _LC1_B5 &  _LC2_B5;

-- Node name is '|ADD:1|LPM_ADD_SUB:102|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B8', type is buried 
_LC7_B8  = LCELL( _EQ009);
  _EQ009 =  _LC1_B8 &  _LC2_B9;

-- Node name is '|ADD:1|LPM_ADD_SUB:102|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B8', type is buried 
_LC8_B8  = LCELL( _EQ010);
  _EQ010 =  _LC2_B8 &  _LC7_B8;

-- Node name is '|ADD:1|:18' = '|ADD:1|tmp0' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = DFFE( _EQ011,  clk,  VCC,  VCC,  VCC);
  _EQ011 =  clk1 & !_LC2_B10
         # !clk1 &  _LC2_B10;

-- Node name is '|ADD:1|:17' = '|ADD:1|tmp1' 
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = DFFE( _EQ012,  clk,  VCC,  VCC,  VCC);
  _EQ012 = !clk1 & !_LC5_B5
         #  _LC2_B10 & !_LC5_B5
         #  clk1 & !_LC2_B10 &  _LC5_B5;

-- Node name is '|ADD:1|:16' = '|ADD:1|tmp2' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = DFFE( _EQ013,  clk,  VCC,  VCC,  VCC);
  _EQ013 = !clk1 & !_LC4_B5 &  _LC5_B5
         #  clk1 & !_LC2_B10 &  _LC4_B5
         #  _LC4_B5 & !_LC5_B5
         #  _LC2_B10 & !_LC4_B5 &  _LC5_B5;

-- Node name is '|ADD:1|:15' = '|ADD:1|tmp3' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = DFFE( _EQ014,  clk,  VCC,  VCC,  VCC);
  _EQ014 = !clk1 &  _LC3_B5 & !_LC7_B5
         # !clk1 & !_LC3_B5 &  _LC7_B5
         #  clk1 &  _LC3_B5 & !_LC8_B5
         #  clk1 & !_LC3_B5 &  _LC8_B5;

-- Node name is '|ADD:1|:14' = '|ADD:1|tmp4' 
-- Equation name is '_LC1_B5', type is buried 
_LC1_B5  = DFFE( _EQ015,  clk,  VCC,  VCC,  VCC);
  _EQ015 =  clk1 &  _LC1_B5 & !_LC2_B5
         #  clk1 & !_LC1_B5 &  _LC2_B5
         # !clk1 &  _LC1_B5 & !_LC6_B5
         # !clk1 & !_LC1_B5 &  _LC6_B5;

-- Node name is '|ADD:1|:13' = '|ADD:1|tmp5' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = DFFE( _EQ016,  clk,  VCC,  VCC,  VCC);
  _EQ016 =  clk1 &  _LC1_B8 & !_LC2_B9
         #  clk1 & !_LC1_B8 &  _LC2_B9
         # !clk1 &  _LC1_B8 & !_LC4_B8
         # !clk1 & !_LC1_B8 &  _LC4_B8;

-- Node name is '|ADD:1|:12' = '|ADD:1|tmp6' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = DFFE( _EQ017,  clk,  VCC,  VCC,  VCC);
  _EQ017 = !clk1 &  _LC2_B8 & !_LC5_B8
         # !clk1 & !_LC2_B8 &  _LC5_B8
         #  clk1 &  _LC2_B8 & !_LC7_B8
         #  clk1 & !_LC2_B8 &  _LC7_B8;

-- Node name is '|ADD:1|:11' = '|ADD:1|tmp7' 
-- Equation name is '_LC3_B8', type is buried 
_LC3_B8  = DFFE( _EQ018,  clk,  VCC,  VCC,  VCC);
  _EQ018 = !clk1 &  _LC3_B8 & !_LC6_B8
         # !clk1 & !_LC3_B8 &  _LC6_B8
         #  clk1 &  _LC3_B8 & !_LC8_B8
         #  clk1 & !_LC3_B8 &  _LC8_B8;

-- Node name is '|sin:6|LPM_ROM:1|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_B', type is memory 
_EC2_B   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC2_B10, _LC5_B5, _LC4_B5, _LC3_B5, _LC1_B5, _LC1_B8, _LC2_B8, _LC3_B8, VCC, VCC, VCC,);

-- Node name is '|sin:6|LPM_ROM:1|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC7_B', type is memory 
_EC7_B   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC2_B10, _LC5_B5, _LC4_B5, _LC3_B5, _LC1_B5, _LC1_B8, _LC2_B8, _LC3_B8, VCC, VCC, VCC,);

-- Node name is '|sin:6|LPM_ROM:1|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_B', type is memory 
_EC3_B   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC2_B10, _LC5_B5, _LC4_B5, _LC3_B5, _LC1_B5, _LC1_B8, _LC2_B8, _LC3_B8, VCC, VCC, VCC,);

-- Node name is '|sin:6|LPM_ROM:1|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_B', type is memory 
_EC1_B   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC2_B10, _LC5_B5, _LC4_B5, _LC3_B5, _LC1_B5, _LC1_B8, _LC2_B8, _LC3_B8, VCC, VCC, VCC,);

-- Node name is '|sin:6|LPM_ROM:1|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC6_B', type is memory 
_EC6_B   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC2_B10, _LC5_B5, _LC4_B5, _LC3_B5, _LC1_B5, _LC1_B8, _LC2_B8, _LC3_B8, VCC, VCC, VCC,);

-- Node name is '|sin:6|LPM_ROM:1|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC8_B', type is memory 
_EC8_B   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC2_B10, _LC5_B5, _LC4_B5, _LC3_B5, _LC1_B5, _LC1_B8, _LC2_B8, _LC3_B8, VCC, VCC, VCC,);

-- Node name is '|sin:6|LPM_ROM:1|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_B', type is memory 
_EC4_B   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC2_B10, _LC5_B5, _LC4_B5, _LC3_B5, _LC1_B5, _LC1_B8, _LC2_B8, _LC3_B8, VCC, VCC, VCC,);

-- Node name is '|sin:6|LPM_ROM:1|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC5_B', type is memory 
_EC5_B   = MEMORY_SEGMENT( VCC, VCC, VCC, GND, VCC, _LC2_B10, _LC5_B5, _LC4_B5, _LC3_B5, _LC1_B5, _LC1_B8, _LC2_B8, _LC3_B8, VCC, VCC, VCC,);



Project Information                             d:\max2work\dac0832\sintop.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,174K