📄 sintop.rpt
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Total single-pin Output Enables required: 0
Logic cells inserted for fitting: 8
Synthesized logic cells: 8/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 8 0 0 8 1 1 0 0 8 0 1 0 0 0 1 0 0 1 0 1 0 22/8
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 4/0
Total: 0 0 0 0 8 0 0 8 1 1 0 0 8 1 2 0 0 0 1 0 0 2 0 2 0 26/8
Device-Specific Information: d:\max2work\dac0832\sintop.rpt
sintop
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
72 - - A -- INPUT 0 0 0 8 clk
2 - - - -- INPUT 0 0 0 8 clk1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max2work\dac0832\sintop.rpt
sintop
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
65 - - B -- OUTPUT 0 1 0 0 data0
64 - - B -- OUTPUT 0 1 0 0 data1
62 - - C -- OUTPUT 0 1 0 0 data2
61 - - C -- OUTPUT 0 1 0 0 data3
60 - - C -- OUTPUT 0 1 0 0 data4
59 - - C -- OUTPUT 0 1 0 0 data5
58 - - C -- OUTPUT 0 1 0 0 data6
54 - - - 21 OUTPUT 0 1 0 0 data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max2work\dac0832\sintop.rpt
sintop
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 05 AND2 0 2 0 1 |ADD:1|LPM_ADD_SUB:61|addcore:adder|:125
- 6 - B 05 AND2 0 3 0 1 |ADD:1|LPM_ADD_SUB:61|addcore:adder|:129
- 4 - B 08 AND2 0 4 0 2 |ADD:1|LPM_ADD_SUB:61|addcore:adder|:133
- 5 - B 08 AND2 0 2 0 2 |ADD:1|LPM_ADD_SUB:61|addcore:adder|:137
- 6 - B 08 AND2 0 2 0 1 |ADD:1|LPM_ADD_SUB:61|addcore:adder|:141
- 8 - B 05 AND2 0 3 0 1 |ADD:1|LPM_ADD_SUB:102|addcore:adder|:125
- 2 - B 05 AND2 0 4 0 2 |ADD:1|LPM_ADD_SUB:102|addcore:adder|:129
- 2 - B 09 AND2 0 2 0 2 |ADD:1|LPM_ADD_SUB:102|addcore:adder|:133
- 7 - B 08 AND2 0 2 0 2 |ADD:1|LPM_ADD_SUB:102|addcore:adder|:137
- 8 - B 08 AND2 0 2 0 1 |ADD:1|LPM_ADD_SUB:102|addcore:adder|:141
- 3 - B 08 DFFE 2 2 0 8 |ADD:1|tmp7 (|ADD:1|:11)
- 2 - B 08 DFFE 2 2 0 10 |ADD:1|tmp6 (|ADD:1|:12)
- 1 - B 08 DFFE 2 2 0 10 |ADD:1|tmp5 (|ADD:1|:13)
- 1 - B 05 DFFE 2 2 0 10 |ADD:1|tmp4 (|ADD:1|:14)
- 3 - B 05 DFFE 2 2 0 11 |ADD:1|tmp3 (|ADD:1|:15)
- 4 - B 05 DFFE 2 2 0 13 |ADD:1|tmp2 (|ADD:1|:16)
- 5 - B 05 DFFE 2 1 0 14 |ADD:1|tmp1 (|ADD:1|:17)
- 2 - B 10 DFFE 2 0 0 12 |ADD:1|tmp0 (|ADD:1|:18)
- 8 - B 18 SOFT s r 0 1 1 0 data0~fit~in1
- 7 - B 14 SOFT s r 0 1 1 0 data1~fit~in1
- 1 - C 21 SOFT s r 0 1 1 0 data2~fit~in1
- 3 - C 23 SOFT s r 0 1 1 0 data3~fit~in1
- 4 - B 23 SOFT s r 0 1 1 0 data4~fit~in1
- 8 - C 14 SOFT s r 0 1 1 0 data5~fit~in1
- 7 - C 13 SOFT s r 0 1 1 0 data6~fit~in1
- 2 - B 21 SOFT s r 0 1 1 0 data7~fit~in1
- - 2 B -- MEM_SGMT 0 8 0 1 |sin:6|LPM_ROM:1|altrom:srom|segment0_0
- - 7 B -- MEM_SGMT 0 8 0 1 |sin:6|LPM_ROM:1|altrom:srom|segment0_1
- - 3 B -- MEM_SGMT 0 8 0 1 |sin:6|LPM_ROM:1|altrom:srom|segment0_2
- - 1 B -- MEM_SGMT 0 8 0 1 |sin:6|LPM_ROM:1|altrom:srom|segment0_3
- - 6 B -- MEM_SGMT 0 8 0 1 |sin:6|LPM_ROM:1|altrom:srom|segment0_4
- - 8 B -- MEM_SGMT 0 8 0 1 |sin:6|LPM_ROM:1|altrom:srom|segment0_5
- - 4 B -- MEM_SGMT 0 8 0 1 |sin:6|LPM_ROM:1|altrom:srom|segment0_6
- - 5 B -- MEM_SGMT 0 8 0 1 |sin:6|LPM_ROM:1|altrom:srom|segment0_7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\max2work\dac0832\sintop.rpt
sintop
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 10/ 48( 20%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\max2work\dac0832\sintop.rpt
sintop
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\max2work\dac0832\sintop.rpt
sintop
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
-- Node name is 'data0~fit~in1'
-- Equation name is 'data0~fit~in1', location is LC8_B18, type is buried.
-- synthesized logic cell
_LC8_B18 = LCELL( _EC2_B);
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC8_B18;
-- Node name is 'data1~fit~in1'
-- Equation name is 'data1~fit~in1', location is LC7_B14, type is buried.
-- synthesized logic cell
_LC7_B14 = LCELL( _EC7_B);
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC7_B14;
-- Node name is 'data2~fit~in1'
-- Equation name is 'data2~fit~in1', location is LC1_C21, type is buried.
-- synthesized logic cell
_LC1_C21 = LCELL( _EC3_B);
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC1_C21;
-- Node name is 'data3~fit~in1'
-- Equation name is 'data3~fit~in1', location is LC3_C23, type is buried.
-- synthesized logic cell
_LC3_C23 = LCELL( _EC1_B);
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC3_C23;
-- Node name is 'data4~fit~in1'
-- Equation name is 'data4~fit~in1', location is LC4_B23, type is buried.
-- synthesized logic cell
_LC4_B23 = LCELL( _EC6_B);
-- Node name is 'data4'
-- Equation name is 'data4', type is output
data4 = _LC4_B23;
-- Node name is 'data5~fit~in1'
-- Equation name is 'data5~fit~in1', location is LC8_C14, type is buried.
-- synthesized logic cell
_LC8_C14 = LCELL( _EC8_B);
-- Node name is 'data5'
-- Equation name is 'data5', type is output
data5 = _LC8_C14;
-- Node name is 'data6~fit~in1'
-- Equation name is 'data6~fit~in1', location is LC7_C13, type is buried.
-- synthesized logic cell
_LC7_C13 = LCELL( _EC4_B);
-- Node name is 'data6'
-- Equation name is 'data6', type is output
data6 = _LC7_C13;
-- Node name is 'data7~fit~in1'
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