plltop.vams

phase frequency detector verilog

// Phase Locked Loop
//
// Version 1a, 1 June 04
//
// Olaf Zinke
//
// Downloaded from The Designer's Guide Community (www.designers-guide.org).
// Post any questions on www.designers-guide.org/Forum.
// Taken from "The Designer's Guide to Verilog-AMS" by Kundert & Zinke.
// Appendix A, Listing 4.

`include "constants.vams"
`include "disciplines.vams"
`timescale 10ps / 1ps

module plltop ();
    electrical gnd;
    ground gnd;
    reg ref, reset;

    initial begin
	ref = 0;
	reset = 1;
	#100
	reset = 0;
    end
    always #3333 ref = ~ref;  // 15MHz

    pfd PFD (.reset(reset), .qinc(up), .active(fb) , .ref(ref), .qdec(dwn));
    cp #(.cur(1m)) CP (.nout(gnd), .dec(dwn), .inc(up), .pout(err));
    capacitor #(.c(30n)) C (err, err2);
    resistor #(.r(200)) R (err2, gnd);
    vco #(.f0(1.5E9), .kvco(50.0E6), .rin(100k)) VCO (.ps(err), .ns(gnd), .out(out));
    fd FD (.reset(reset), .out(fb), .clk(out));
endmodule