skyeye_mach_omap5912.c

skyeye for pxa270

#include <sys/time.h>
#include <sys/types.h>
#include <unistd.h>

#include "armdefs.h"
#include "omap5912.h"

/*ywc 2005-03-30*/
#include "skyeye_flash.h"

/* 2007-01-18 added by Anthony Lee : for new uart device frame */
#include "skyeye_uart.h"

//ywc,2004-11-30,declare a external array which stores touchscreen event information
extern unsigned int Pen_buffer[8];	// defined in skyeye_lcd.c
//ywc,2004-11-30,declare a external array which stores touchscreen event information,end

//define omap uart interrupt type
#define REC_LINE_STA	0x6
#define RX_TM_OUT	0xc
#define RHR_INT		0x4
#define THR_INT		0x2
//chy 2005-09-19, the define of omap27x_io_t is in omap.h
//static omap5912_io_t omap5912_io;
static struct omap5912_io_t omap5912_io;

static void
omap5912_io_reset ()
{
	memset(&omap5912_io, 0, sizeof(struct omap5912_io_t));
#if 1
	omap5912_io.timer.mpu_read_timer[0] = 0xea5f/500;
	omap5912_io.timer.mpu_load_timer[0] = 0xea5f/500;
	omap5912_io.timer.mpu_read_timer[1] = 0xffffffff/(50*1024*1024);
	omap5912_io.timer.mpu_load_timer[1] = 0xffffffff/(50*1024*1024);
#endif
#if 1
	omap5912_io.uart.lsr = 0x60;
	omap5912_io.uart.iir = 0x1;
	omap5912_io.uart.tcr = 0xf;
	omap5912_io.uart.mdr1 = 0x7;
	omap5912_io.uart.blr = 0x40;
	omap5912_io.uart.wer = 0x7f;
#endif
	omap5912_io.uart.msr = 0x90;
	
	omap5912_io.os_timer.os_timer_tick_cntr = (0xff);

	omap5912_io.ic.mpu_l2_mir = 0xffffffff;
	omap5912_io.ic.mpu_l2_itr = 0x0;
	omap5912_io.ic.mpu_l1_mir = 0xffffffff;
	omap5912_io.ic.mpu_l1_itr = 0x0;
}
static
omap_set_intr (u32 interrupt)
{
}

static int
omap_pending_intr (u32 interrupt)
{
}

static void
omap5912_update_l2_int (ARMul_State * state)
{
	ARMword requests;
	int i;	
	//printf(" here mpu2_itr data = %x\n", omap5912_io.ic.mpu_l2_itr);
	requests = omap5912_io.ic.mpu_l2_itr & ((~omap5912_io.ic.mpu_l2_mir) & 0xffffffff);
//	printf("mpu2 requests %x\n",requests);
//	printf(" here mpu1_itr data = %x\n", omap5912_io.ic.mpu_l1_itr);

	if ((requests & (1<<14)))			       //uart1 14
	{
		omap5912_io.ic.mpu_l1_itr |= 0x1;             //l2 interrupt mapped to l1 IRQ0
		//printf("requests_l2_test\n");
	}
	#if 1
		for (i=31; i>=0; i--)
		{
			if (omap5912_io.ic.mpu_l1_itr & (1 << i))
				break;
		}
		if (i <=31)
		{
			omap5912_io.ic.mpu_l1_sir_irq_code = i;
		}
	#endif
//	printf(" here mpu1_itr data = %x\n", omap5912_io.ic.mpu_l1_itr);
}

static void
omap5912_update_int (ARMul_State * state)
{
	//uart1 and os timer int is mapped to l2 int
        ARMword requests;

	//printf("irq sig initial: %x\n", state->NirqSig);
	omap5912_update_l2_int(state);

	//printf(" here test  mpu1_itr data = %x\n", omap5912_io.ic.mpu_l1_itr);
	requests = omap5912_io.ic.mpu_l1_itr & ((~omap5912_io.ic.mpu_l1_mir) & 0xffffffff);
	//printf("requests %x\n",requests);
	state->NirqSig = (requests) ? LOW : HIGH;
	state->NfiqSig = HIGH;

	//printf("irq sig in l1:%x\n", state->NirqSig);

}

static void
omap_update_intr (void *mach)
{
        struct machine_config *mc = (struct machine_config *) mach;
        ARMul_State *state = (ARMul_State *) mc->state;
	omap5912_update_int(state);
}


static void
omap5912_io_do_cycle (ARMul_State * state)
{
	struct timeval tv;
	unsigned char buf;
	int i = 0;

	tv.tv_sec = 0;
	tv.tv_usec = 0;
	/** mpu timer interrupt update*/
#if 1
		if ((omap5912_io.timer.mpu_cntl_timer[0] & 0x23) == 0x23) //bit5 enable clock; bit1 auto or oneshot;bit0 start decrem
		{
			//omap5912_io.timer.mpu_read_timer[0] &= 0x0000000f;
			omap5912_io.timer.mpu_read_timer[0]--;
			//printf("omap5912_io.timer.mpu_load_timer[0] = %x\n",omap5912_io.timer.mpu_load_timer[0]);
			//printf("omap5912_io.timer.mpu_read_timer[0] = %x\n",omap5912_io.timer.mpu_read_timer[0]);

			if (omap5912_io.timer.mpu_read_timer[0] == 0)
			{
				//printf("omap5912_io.timer.mpu_read_timer[0] = %x\n",omap5912_io.timer.mpu_read_timer[0]);
				omap5912_io.timer.mpu_read_timer[0] = (omap5912_io.timer.mpu_load_timer[0]);

				//printf("omap5912_io.timer.mpu_read_timer[0] = %x\n",omap5912_io.timer.mpu_read_timer[0]);
				omap5912_io.ic.mpu_l1_itr |= (1 << 26);
				/*shoulod add some code to determin which priority the interrpt is!1*/
		#if 1
				for (i=31; i>=0; i--)
				{
					if (omap5912_io.ic.mpu_l1_itr & (1 << i))
						break;
				}
				if (i <=31)
				{
					omap5912_io.ic.mpu_l1_sir_irq_code = i;
					//omap5912_io.ic.mpu_l1_itr &= ~(1 << i);
				}
		#endif
				omap5912_update_int(state);
				return;
			}	
			//omap5912_update_int(state);
		}
#endif

	/*uart interrupt update*/
#if 0
	if ((omap5912_io.uart.ier & 0xf) == 0x5)
	{
		//printf("uart_lsr%x\n", omap5912_io.uart.lsr);
		//printf("uart_ier%x\n", omap5912_io.uart.ier);
		if (skyeye_uart_read(-1, &buf, 1, &tv, NULL) > 0)
		{
			//if (buf == 1) buf = 3;

			//printf("buf%x\n", buf);
			omap5912_io.uart.rhr = buf;
			omap5912_io.uart.lsr |= (0x1); //bit 0: no data in receive bugger
			//omap5912_io.uart.iir |= RHR_INT;
		}
		//omap5912_io.uart.iir &= 0x0 ;
		if ((omap5912_io.uart.ier & 0x1) && (omap5912_io.uart.lsr & 0x1))
		{
			omap5912_io.uart.iir = RHR_INT;
			omap5912_io.ic.mpu_l2_itr |= (1<<14);
		#if 1
		for (i=31; i>=0; i--)
		{
			if (omap5912_io.ic.mpu_l2_itr & (1 << i))
				break;
		}
		if (i <=31)
		{
			omap5912_io.ic.mpu_l2_sir_irq = i;
			//printf("i = %d\n", i);
		}
		#endif
		}
		omap5912_update_int(state);
		return;
		
	}
#endif
		omap5912_update_int(state);
}

static void
omap5912_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
	omap_ioreg_t ioregaddr = addr;

#if 1
	if ((addr >= UART1_RHR) && (addr <= UART1_WER))
	{
		switch (addr) { 
		/**uart 1*/
		case UART1_THR:
		{	
			int i;
			//omap5912_io.uart.thr = data;
			//omap5912_io.uart.dll = data;
			unsigned char c = data;
			if (skyeye_uart_write(-1, &c, 1, NULL) < 0)
			{
				return;
			}
			//omap5912_io.uart.iir = 0x1;
			omap5912_io.uart.lsr = 0x60;
			//omap5912_io.uart.iir = THR_INT & (0xff);
		#if 1
			//if transmit interrupt comes
			if ((omap5912_io.uart.ier & 0xf) == 0x2)
			//if ((omap5912_io.uart.iir & 0xf) == THR_INT)
			{
				//printf("whyhere\n");
				omap5912_io.ic.mpu_l2_itr |= (1<<14);
				for (i=31; i>=0; i--)
				{	
					if (omap5912_io.ic.mpu_l2_itr & (1 << i))
						break;
				}
				if (i <=31)
				{
					omap5912_io.ic.mpu_l2_sir_irq = i;
				}

				omap5912_update_int(state);
			}
		#endif

		}
			//printf("data in thr=%x\n", data);
			break;
		
		case  UART1_IER:
			omap5912_io.uart.ier = data;
		//	omap5912_io.uart.dlh = data;
		//	printf("data in ier=%x\n", data);
			break;
		case UART1_FCR:
			omap5912_io.uart.fcr = data;
		//	omap5912_io.uart.efr = data;
			break;
		case UART1_LCR:
			omap5912_io.uart.lcr = data;
			break;
		case UART1_MCR:
			omap5912_io.uart.mcr = data;
		//	omap5912_io.uart.xon1 = data;
			break;
		case UART1_XON2:
			omap5912_io.uart.xon2 = data;
			break;
		case UART1_TCR:
			omap5912_io.uart.tcr = data;
			//omap5912_io.uart.xoff1 = data;
			break;
		case UART1_SPR:
			omap5912_io.uart.spr = data;
			//omap5912_io.uart.tlr = data;
			//omap5912_io.uart.xoff2 = data;
			break;
		case UART1_MDR1:
			omap5912_io.uart.mdr1 = data;
			break;
		case UART1_MDR2:
			omap5912_io.uart.mdr2 = data;
			break;
		case UART1_TXFLL:
			omap5912_io.uart.txfll = data;
			break;
		case UART1_TXFLH:
			omap5912_io.uart.txflh = data;
			break;
		case UART1_RXFLL:
			omap5912_io.uart.rxfll = data;
			break;
		case UART1_SFREGH: 
			omap5912_io.uart.sfregh = data;
			//omap5912_io.uart.rxflh = data;
			break;
		case UART1_BLR:
			omap5912_io.uart.blr = data;
			break;
		case UART1_ACREG:
			omap5912_io.uart.acreg = data;
			break;
		case UART1_SCR:
			omap5912_io.uart.scr = data;
			break;
		case UART1_SSR:
			omap5912_io.uart.ssr = data;
			break;
		case UART1_EBLR:
			omap5912_io.uart.eblr = data;
			break;
		case UART1_SYSC:
			omap5912_io.uart.sysc = data;
			break;
		case UART1_SYSS:
			omap5912_io.uart.syss = data;
			break;
		case UART1_WER:
			omap5912_io.uart.wer = data;
			break;
		default:
			break;
		}//?endswitch
	}//endif
#endif	
	if ((ioregaddr >= MPU_L1_ILR0) && (ioregaddr <=MPU_L1_ILR31))
	{
		int offset = (ioregaddr - MPU_L1_ILR0)/4;
		omap5912_io.ic.mpu_l1_ilr[offset] = data;
		//printf("mpu l1 ilr[%d] 0x%x\n",offset,data);
		return;
	}
	if ((ioregaddr >= MPU_L2_ILR0) && (ioregaddr <=MPU_L2_ILR31))
	{
		int offset = (ioregaddr - MPU_L2_ILR0)/4;
		omap5912_io.ic.mpu_l2_ilr[offset] = data;
		//printf("mpu l2 ilr[%d] 0x%x\n",offset/4,data);
		return;
	}
	if ((ioregaddr >= MPU_L2_ILR0_S1) && (ioregaddr <=MPU_L2_ILR31_S1))
	{
		int offset = (ioregaddr - MPU_L2_ILR0_S1)/4;
		omap5912_io.ic.mpu_l2_ilr_s1[offset] = data;
		//printf("mpu l2 ilr[%d] 0x%x\n",offset/4,data);
		return;
	}
	if ((ioregaddr >= MPU_L2_ILR0_S2) && (ioregaddr <=MPU_L2_ILR31_S2))
	{
		int offset = (ioregaddr - MPU_L2_ILR0_S2)/4;
		omap5912_io.ic.mpu_l2_ilr_s2[offset] = data;
		//printf("mpu l2 ilr[%d] 0x%x\n",offset/4,data);
		return;
	}
	if ((ioregaddr >= MPU_L2_ILR0_S3) && (ioregaddr <=MPU_L2_ILR31_S3))
	{
		int offset = (ioregaddr - MPU_L2_ILR0_S3)/4;
		omap5912_io.ic.mpu_l2_ilr_s3[offset] = data;
		//printf("mpu l2 ilr[%d] 0x%x\n",offset/4,data);
		return;
	}

	switch (ioregaddr) { 
		/*os timer*/
		case OS_TIMER_TICK_VAL:
			omap5912_io.os_timer.os_timer_tick_val = data & (0x00ffffff);
			break;
		case OS_TIMER_CTRL:
			omap5912_io.os_timer.os_timer_ctrl = data;
			printf("timeros control register %x\n", data);
			break;
		/*
		case TIMER_32K_SYNCHRONIZED:
			omap5912_io.timer_32k_synchronized = data;
			printf("write 32k synchronized%x\n", data);
			break;
		*/
		/*mpu timer*/
		case MPU_CNTL_TIMER1:
			omap5912_io.timer.mpu_cntl_timer[0] = data;
			break;
		case MPU_LOAD_TIMER1:
			//omap5912_io.timer.mpu_load_timer[0] = 1000/8/6; //what size should be set?
			omap5912_io.timer.mpu_load_timer[0] = data/1000; //what size should be set?
			//printf("timer1 load register %x\n", omap5912_io.timer.mpu_load_timer[0]);
			break;
		case MPU_CNTL_TIMER2:
			omap5912_io.timer.mpu_cntl_timer[1] = data;
			break;
		case MPU_LOAD_TIMER2:
			//omap5912_io.timer.mpu_load_timer[1] = (0xffffffff)/(100*1024*1024); //what size should be set?
			omap5912_io.timer.mpu_load_timer[1] = data; //what size should be set?
			//printf("timer2 load register %x\n", omap5912_io.timer.mpu_load_timer[1]);
			break;
		case MPU_CNTL_TIMER3:
			omap5912_io.timer.mpu_cntl_timer[2] = data;
			break;
		case MPU_LOAD_TIMER3:
			omap5912_io.timer.mpu_load_timer[2] = data;
			break;
		
		/**uart 1*/
#if 0
		case UART1_THR:
		{	omap5912_io.uart.thr = (data & 0xff);
			unsigned char c = (data & 0xff);
			j = skyeye_uart_write(-1, &c, 1, NULL);
			omap5912_io.uart.lsr |= 0x60;
		//	printf("here,j =%d\n", j);
		}
			break;
#endif
		/** interrupt control*/
		case MPU_L2_ITR:
			omap5912_io.ic.mpu_l2_itr = data;
			//printf("write mpu2_itr data = %x\n", data);
			break;
		case MPU_L2_MIR:
			omap5912_io.ic.mpu_l2_mir = data;
			//printf("write mpu2_imr data = %x\n", data);
			break;
		case MPU_L2_CONTROL:
		#if 1
			{
			int i;
			i = omap5912_io.ic.mpu_l2_sir_irq;
			//printf("sirirq i = %x\n", i);
			omap5912_io.ic.mpu_l2_itr &= ~(1 << i);
			}
			#endif

			omap5912_io.ic.mpu_l2_control = data;
			//printf("write mpu2_control data = %x\n", data);
			break;
		case MPU_L2_ISR:
			omap5912_io.ic.mpu_l2_isr = data;
	//	printf("write mpu2_l2 isr data = %x\n", data);
			break;
		case MPU_L2_OCP_CFG:
			omap5912_io.ic.mpu_l2_ocp_cfg = data;
			//printf("write mpu2_l2 ocp cfg  data = %x\n", data);
			break;
		case MPU_L1_ITR:
			omap5912_io.ic.mpu_l1_itr = (data &0xffffffff);
			//printf("write mpu1_itr data = %x\n", data);
			break;
		case MPU_L1_MIR:
			omap5912_io.ic.mpu_l1_mir = data;
			//printf("write mpu1_imr data = %x\n", data);
			break;
		case MPU_L1_CONTROL:
			#if 1