📄 omap5912.h

📁 skyeye for pxa270
💻 H
📖 第 1 页 / 共 3 页
字号:
上一页 1 23
#define MPU_L1_ILR18	(0xFFFECB64)#define MPU_L1_ILR19	(0xFFFECB68)#define MPU_L1_ILR20	(0xFFFECB6C)#define MPU_L1_ILR21	(0xFFFECB70)#define MPU_L1_ILR22	(0xFFFECB74)#define MPU_L1_ILR23	(0xFFFECB78)#define MPU_L1_ILR24	(0xFFFECB7C)#define MPU_L1_ILR25	(0xFFFECB80)#define MPU_L1_ILR26	(0xFFFECB84)#define MPU_L1_ILR27	(0xFFFECB88)#define MPU_L1_ILR28	(0xFFFECB8C)#define MPU_L1_ILR29	(0xFFFECB90)#define MPU_L1_ILR30	(0xFFFECB94)#define MPU_L1_ILR31	(0xFFFECB98)#define MPU_L1_ISR	(0xFFFECB9C)#define MPU_L1_ENHANCEED_CNTL	(0xFFFECBA0)/*********************//* RTC Registers     *//*********************/#define SECONDS_REG	(0xFFFB4800)#define MINUTES_REG	(0xFFFB4804)#define HOURS_REG	(0xFFFB4808)#define DAYS_REG	(0XFFFB480C)#define MONTH_REG	(0xFFFB4810)#define YEAR_REG	(0xFFFB4814)#define WEEK_REG	(0xFFFB4818)#define ALARM_SECONDS_REG	(0xFFFB4820)#define ALARM_MINUTES_REG	(0xFFFB4824)#define ALARM_HOURS_REG		(0xFFFB4828)#define ALARM_DAYS_REG		(0XFFFB482C)#define ALARM_MONTH_REG		(0xFFFB4830)#define ALARM_YEAR_REG		(0xFFFB4834)#define RTC_CTRL_REG		(0xFFFB4840)#define RTC_STATUS_REG		(0xFFFB4844)#define RTC_INTERRUPTS_REG	(0xFFFB4848)#define RTC_COMP_LSB_REG	(0xFFFB484C)#define RTC_COMP_MSB_REG	(0xFFFB4850)#define RTC_OSC_REG		(0xFFFB4854)/***************************//* WatchDog Timer Registers     *//***************************/#define MPU_WDT_CNTL_TIMER	(0xFFFEC800)#define MPU_WDT_LOAD_TIMER	(0xFFFEC804)#define MPU_WDT_READ_TIMER	(0xFFFEC804)#define MPU_WDT_TIMER_TIMER	(0xFFFEC808)/***************************//*MPU Timer Registers     *//***************************/#define MPU_CNTL_TIMER1		(0xFFFEC500)#define MPU_LOAD_TIMER1		(0xFFFEC504)#define MPU_READ_TIMER1		(0xFFFEC508)#define MPU_CNTL_TIMER2		(0xFFFEC600)#define MPU_LOAD_TIMER2		(0xFFFEC604)#define MPU_READ_TIMER2		(0xFFFEC608)#define MPU_CNTL_TIMER3		(0xFFFEC700)#define MPU_LOAD_TIMER3		(0xFFFEC704)#define MPU_READ_TIMER3		(0xFFFEC708)/***************************//* Genearal purpose Timer Registers     *//***************************/#define GPTMR1_TIDR		(0xFFFB1400)#define GPTMR1_TIOCP_CFG	(0xFFFB1410)#define GPTMR1_TISTAT		(0xFFFB1414)#define GPTMR1_TISR		(0xFFFB1418)#define GPTMR1_TIER		(0xFFFB141C)#define GPTMR1_TWER		(0xFFFB1420)#define GPTMR1_TCLR		(0xFFFB1424)#define GPTMR1_TCRR		(0xFFFB1428)#define GPTMR1_TLDR		(0xFFFB142C)#define GPTMR1_TTGR		(0xFFFB1430)#define GPTMR1_TWPS		(0xFFFB1434)#define GPTMR1_TMAR		(0xFFFB1438)#define GPTMR1_TSICR		(0xFFFB1440)#define GPTMR2_TIDR		(0xFFFB1C00)#define GPTMR2_TIOCP_CFG	(0xFFFB1C10)#define GPTMR2_TISTAT		(0xFFFB1C14)#define GPTMR2_TISR		(0xFFFB1C18)#define GPTMR2_TIER		(0xFFFB1C1C)#define GPTMR2_TWER		(0xFFFB1C20)#define GPTMR2_TCLR		(0xFFFB1C24)#define GPTMR2_TCRR		(0xFFFB1C28)#define GPTMR2_TLDR		(0xFFFB1C2C)#define GPTMR2_TTGR		(0xFFFB1C30)#define GPTMR2_TWPS		(0xFFFB1C34)#define GPTMR2_TMAR		(0xFFFB1C38)#define GPTMR2_TSICR		(0xFFFB1C40)#define GPTMR3_TIDR		(0xFFFB2400)#define GPTMR3_TIOCP_CFG	(0xFFFB2410)#define GPTMR3_TISTAT		(0xFFFB2414)#define GPTMR3_TISR		(0xFFFB2418)#define GPTMR3_TIER		(0xFFFB241C)#define GPTMR3_TWER		(0xFFFB2420)#define GPTMR3_TCLR		(0xFFFB2424)#define GPTMR3_TCRR		(0xFFFB2428)#define GPTMR3_TLDR		(0xFFFB242C)#define GPTMR3_TTGR		(0xFFFB2430)#define GPTMR3_TWPS		(0xFFFB2434)#define GPTMR3_TMAR		(0xFFFB2438)#define GPTMR3_TSICR		(0xFFFB2440)#define GPTMR4_TIDR		(0xFFFB2C00)#define GPTMR4_TIOCP_CFG	(0xFFFB2C10)#define GPTMR4_TISTAT		(0xFFFB2C14)#define GPTMR4_TISR		(0xFFFB2C18)#define GPTMR4_TIER		(0xFFFB2C1C)#define GPTMR4_TWER		(0xFFFB2C20)#define GPTMR4_TCLR		(0xFFFB2C24)#define GPTMR4_TCRR		(0xFFFB2C28)#define GPTMR4_TLDR		(0xFFFB2C2C)#define GPTMR4_TTGR		(0xFFFB2C30)#define GPTMR4_TWPS		(0xFFFB2C34)#define GPTMR4_TMAR		(0xFFFB2C38)#define GPTMR4_TSICR		(0xFFFB2C40)#define GPTMR5_TIDR		(0xFFFB3400)#define GPTMR5_TIOCP_CFG	(0xFFFB3410)#define GPTMR5_TISTAT		(0xFFFB3414)#define GPTMR5_TISR		(0xFFFB3418)#define GPTMR5_TIER		(0xFFFB341C)#define GPTMR5_TWER		(0xFFFB3420)#define GPTMR5_TCLR		(0xFFFB3424)#define GPTMR5_TCRR		(0xFFFB3428)#define GPTMR5_TLDR		(0xFFFB342C)#define GPTMR5_TTGR		(0xFFFB3430)#define GPTMR5_TWPS		(0xFFFB3434)#define GPTMR5_TMAR		(0xFFFB3438)#define GPTMR5_TSICR		(0xFFFB3440)#define GPTMR6_TIDR		(0xFFFB3C00)#define GPTMR6_TIOCP_CFG	(0xFFFB3C10)#define GPTMR6_TISTAT		(0xFFFB3C14)#define GPTMR6_TISR		(0xFFFB3C18)#define GPTMR6_TIER		(0xFFFB3C1C)#define GPTMR6_TWER		(0xFFFB3C20)#define GPTMR6_TCLR		(0xFFFB3C24)#define GPTMR6_TCRR		(0xFFFB3C28)#define GPTMR6_TLDR		(0xFFFB3C2C)#define GPTMR6_TTGR		(0xFFFB3C30)#define GPTMR6_TWPS		(0xFFFB3C34)#define GPTMR6_TMAR		(0xFFFB3C38)#define GPTMR6_TSICR		(0xFFFB3C40)#define GPTMR7_TIDR		(0xFFFB7400)#define GPTMR7_TIOCP_CFG	(0xFFFB7410)#define GPTMR7_TISTAT		(0xFFFB7414)#define GPTMR7_TISR		(0xFFFB7418)#define GPTMR7_TIER		(0xFFFB741C)#define GPTMR7_TWER		(0xFFFB7420)#define GPTMR7_TCLR		(0xFFFB7424)#define GPTMR7_TCRR		(0xFFFB7428)#define GPTMR7_TLDR		(0xFFFB742C)#define GPTMR7_TTGR		(0xFFFB7430)#define GPTMR7_TWPS		(0xFFFB7434)#define GPTMR7_TMAR		(0xFFFB7438)#define GPTMR7_TSICR		(0xFFFB7440)#define GPTMR8_TIDR		(0xFFFBD400)#define GPTMR8_TIOCP_CFG	(0xFFFBD410)#define GPTMR8_TISTAT		(0xFFFBD414)#define GPTMR8_TISR		(0xFFFBD418)#define GPTMR8_TIER		(0xFFFBD41C)#define GPTMR8_TWER		(0xFFFBD420)#define GPTMR8_TCLR		(0xFFFBD424)#define GPTMR8_TCRR		(0xFFFBD428)#define GPTMR8_TLDR		(0xFFFBD42C)#define GPTMR8_TTGR		(0xFFFBD430)#define GPTMR8_TWPS		(0xFFFBD434)#define GPTMR8_TMAR		(0xFFFBD438)#define GPTMR8_TSICR		(0xFFFBD440)#define SYNC_CNT_REV		(0xFFFBD400)#define K_SYNC_CNT_CR		(0xFFFBD410)#define OS_TIMER_TICK_VAL	(0xFFFB9000)#define OS_TIMER_TICK_CNTR	(0xFFFB9004)#define OS_TIMER_CTRL		(0xFFFB9008)#define TIMER_32K_SYNCHRONIZED 	(0xFFFBC410)/** mpu configure register*/#define ULPD_CLOCK_CTRL		(0xFFFE0830)#define SOFT_REQ_REG		(0xFFFE0834)#define SOFT_REQ_REG2		(0xFFFE0880)#define MOD_CONF_CTRL_0 	(0xFFFE1080)#define FUNC_MUX_CTRL_10	(0xFFFE1098)#define PULL_DWN_CTRL_4		(0xFFFE10AC)#define EMIFS_CS1_CONFIG	(0xFFFECC14)#define DIE_ID_LSB		(0xFFFE1800)#define DIE_ID_MSB		(0xFFFE1804)#define PROD_ID_REG0		(0xFFFE2000)#define PROD_ID_REG1		(0xFFFE2004)#define ARM_CKCTL 		(0xFFFECE00)#define	ARM_IDLECT1  		(0xFFFECE04)#define	ARM_IDLECT2  		(0xFFFECE08)#define ARM_RSTCT1		(0xFFFECE10)#define ARM_RSTCT2		(0xFFFECE14)#define ARM_SYSST		(0xFFFECE18)#define DPLL1_CTL_REG		(0xFFFECF00)struct omap5912_mpu_cfg{	u32 ulpd_clock_ctrl;	u32 soft_req_reg;	u32 soft_req_reg2;	u32 mod_conf_ctrl_0;	u32 func_mux_ctrl_10;	u32 pull_dwn_ctrl_4;	u32 emifs_cs1_config;	u32 die_id_lsb;	u32 die_id_msb;	u32 prod_id_reg0;	u32 prod_id_reg1;	u32 arm_ckctl;	u32 arm_idlect1;	u32 arm_idlect2;	u32 arm_rstct1;	u32 arm_rstct2;	u32 arm_sysst;	u32 dpll1_ctl_reg;};struct omap5912x_gp_timer_io{	u32 tidr;	u32 tiocp_cfg;	u32 tistat;	u32 tisr;	u32 tier;	u32 twer;	u32 tclr;	u32 tcrr;	u32 tldr;	u32 ttgr;	u32 twps;	u32 tmar;	u32 tsicr;};struct omap5912_os_timer{	u32 os_timer_tick_val;	u32 os_timer_tick_cntr;	u32 os_timer_ctrl;};struct omap5912_mpu_timer{	u32 mpu_cntl_timer[3];	u32 mpu_load_timer[3];	u32 mpu_read_timer[3];};struct omap5912_uart{	u32 rhr;	u32 thr;	u32 dll;	u32 ier;	u32 dlh;	u32 iir;	u32 fcr;	u32 efr;	u32 lcr;	u32 mcr;	u32 xon1;	u32 lsr;	u32 xon2;	u32 msr;	u32 tcr;	u32 xoff1;	u32 spr;	u32 tlr;	u32 xoff2;	u32 mdr1;	u32 mdr2;	u32 sflsr;	u32 txfll;	u32 resume;	u32 txflh;	u32 sfregl;	u32 rxfll;	u32 sfregh;	u32 rxflh;	u32 uasr;	u32 blr;	u32 acreg;	u32 scr;	u32 ssr;	u32 eblr;	u32 mvr;	u32 sysc;	u32 syss;	u32 wer;};struct omap5912_ic{	/*interrupt level 2*/	u32 mpu_l2_itr;	u32 mpu_l2_mir;	u32 mpu_l2_sir_irq;	u32 mpu_l2_sir_fiq;	u32 mpu_l2_control;	u32 mpu_l2_ilr[32];	u32 mpu_l2_ilr_s1[32];	u32 mpu_l2_ilr_s2[32];	u32 mpu_l2_ilr_s3[32];	u32 mpu_l2_isr;	u32 mpu_l2_status;	u32 mpu_l2_ocp_cfg;	u32 mpu_l2_inth_rev;	u32 mpu_l2_itr_s1;	u32 mpu_l2_mir_s1;	u32 mpu_l2_sir_irq_s1;	u32 mpu_l2_sir_fiq_s1;	u32 mpu_l2_control_s1;	u32 mpu_l2_itr_s2;	u32 mpu_l2_mir_s2;	u32 mpu_l2_sir_irq_s2;	u32 mpu_l2_sir_fiq_s2;	u32 mpu_l2_control_s2;	u32 mpu_l2_itr_s3;	u32 mpu_l2_mir_s3;	u32 mpu_l2_sir_irq_s3;	u32 mpu_l2_sir_fiq_s3;	u32 mpu_l2_control_s3;	/*interrupt level 1*/	u32 mpu_l1_itr;	u32 mpu_l1_mir;	u32 mpu_l1_sir_irq_code;	u32 mpu_l1_sir_fiq_code;	u32 mpu_l1_ilr[32];	u32 mpu_l1_control;	u32 mpu_l1_isr;	u32 mpu_l1_enhanceed_cntl;};struct omap5912_gpio{	u32 gpio_reversion;	u32 gpio_sysconfig;	u32 gpio_sysstatus;	u32 gpio_irqstatus1;	u32 gpio_irqenable1;	u32 gpio_irqstatus2;	u32 gpio_irqenable2;	u32 gpio_wakeupenable;	u32 gpio_datain;	u32 gpio_dataout;	u32 gpio_direction;	u32 gpio_edge_ctrl1;	u32 gpio_edge_ctrl2;	u32 gpio_clear_irqenable1;	u32 gpio_clear_irqenable2;	u32 gpio_clear_wakeupena;	u32 gpio_clear_dataout;	u32 gpio_set_irqenable1;	u32 gpio_set_irqenable2;	u32 gpio_set_wakeupena;	u32 gpio_set_dataout;};struct omap5912_io_t{	struct omap5912_mpu_timer timer;	struct omap5912_os_timer os_timer;	struct omap5912_uart	uart;	struct omap5912_ic	ic;	struct omap5912_gpio	gpio[4];	struct omap5912_mpu_cfg mpu_cfg; 	u32 timer_32k_synchronized;	};#endif /* __OMAP5912_H_ */
上一页 1 23
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -