📄 omap5912.h

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	ULPD_CLOCK_CTRL	= 0xFFFE0830,	SOFT_REQ_REG = 0xFFFE0834,	SOFT_REQ_REG2 = 0xFFFE0880,	MOD_CONF_CTRL_0 = 0xFFFE1080,	FUNC_MUX_CTRL_10= 0xFFFE1098,	PULL_DWN_CTRL_4	= 0xFFFE10AC,	EMIFS_CS1_CONFIG = 0xFFFECC14,	DIE_ID_LSB = 0xFFFE1800,	DIE_ID_MSB = 0xFFFE1804,	PROD_ID_REG0 = 0xFFFE2000,	PROD_ID_REG1 = 0xFFFE2004,	ARM_CKCTL = 0xFFFECE00,	ARM_IDLECT1 = 0xFFFECE04,	ARM_IDLECT2 = 0xFFFECE08,	ARM_RSTCT1 = 0xFFFECE10,	ARM_RSTCT2 = 0xFFFECE14,	ARM_SYSST = 0xFFFECE18,	DPLL1_CTL_REG = 0xFFFECF00}omap_ioreg_t;#define REGW(addr)	(*(volatile unsigned int *)(addr))/********************************************* Memory Controller Registers********************************************/#define NOR_FLASH		(0x0C000000)#define SDRAM_EXTERNAL		(0x10000000)#define FRAME_BUFFER		(0x20000000)#define TI_CAMERA_IF		(0x3007D800)#define OMAP5912_PERIPHERALS	(0xFFFB0000)/********************************************* LCD Controller Registers********************************************//********************************************* GPIO Controller Registers********************************************/#define GPIO1_REVISION		(0xFFFBE400)#define GPIO1_SYSCONFIG		(0xFFFBE410)#define GPIO1_SYSSTATUS		(0xFFFBE414)#define GPIO1_IRQSTATUS1	(0xFFFBE418)#define GPIO1_IRQENABLE1	(0xFFFBE41C)#define GPIO1_IRQSTATUS2	(0xFFFBE420)#define GPIO1_IRQENABLE2	(0xFFFBE424)#define GPIO1_WAKEUPENABLE	(0xFFFBE428)#define GPIO1_DATAIN		(0xFFFBE42C)#define GPIO1_DATAOUT		(0xFFFBE430)#define GPIO1_DIRECTION		(0xFFFBE434)#define GPIO1_EDGE_CTRL1	(0xFFFBE438)#define GPIO1_EDGE_CTRL2	(0xFFFBE43C)#define GPIO1_CLEAR_IRQENABLE1	(0xFFFBE49C)#define GPIO1_CLEAR_IRQENABLE2	(0xFFFBE4A4)#define GPIO1_CLEAR_WAKEUPENA	(0xFFFBE4A8)#define GPIO1_CLEAR_DATAOUT	(0xFFFBE4B0)#define GPIO1_SET_IRQENABLE1	(0xFFFBE4DC)#define GPIO1_SET_IRQENABLE2	(0xFFFBE4E4)#define GPIO1_SET_WAKEUPENA	(0xFFFBE4E8)#define GPIO1_SET_DATAOUT	(0xFFFBE4F0)#define GPIO2_REVISION		(0xFFFBEC00)#define GPIO2_SYSCONFIG		(0xFFFBEC10)#define GPIO2_SYSSTATUS		(0xFFFBEC14)#define GPIO2_IRQSTATUS1	(0xFFFBEC18)#define GPIO2_IRQENABLE1	(0xFFFBEC1C)#define GPIO2_IRQSTATUS2	(0xFFFBEC20)#define GPIO2_IRQENABLE2	(0xFFFBEC24)#define GPIO2_WAKEUPENABLE	(0xFFFBEC28)#define GPIO2_DATAIN		(0xFFFBEC2C)#define GPIO2_DATAOUT		(0xFFFBEC30)#define GPIO2_DIRECTION		(0xFFFBEC34)#define GPIO2_EDGE_CTRL1	(0xFFFBEC38)#define GPIO2_EDGE_CTRL2	(0xFFFBEC3C)#define GPIO2_CLEAR_IRQENABLE1	(0xFFFBEC9C)#define GPIO2_CLEAR_IRQENABLE2	(0xFFFBECA4)#define GPIO2_CLEAR_WAKEUPENA	(0xFFFBECA8)#define GPIO2_CLEAR_DATAOUT	(0xFFFBECB0)#define GPIO2_SET_IRQENABLE1	(0xFFFBECDC)#define GPIO2_SET_IRQENABLE2	(0xFFFBECE4)#define GPIO2_SET_WAKEUPENA	(0xFFFBECE8)#define GPIO2_SET_DATAOUT	(0xFFFBECF0)#define GPIO3_REVISION		(0xFFFBB400)#define GPIO3_SYSCONFIG		(0xFFFBB410)#define GPIO3_SYSSTATUS		(0xFFFBB414)#define GPIO3_IRQSTATUS1	(0xFFFBB418)#define GPIO3_IRQENABLE1	(0xFFFBB41C)#define GPIO3_IRQSTATUS2	(0xFFFBB420)#define GPIO3_IRQENABLE2	(0xFFFBB424)#define GPIO3_WAKEUPENABLE	(0xFFFBB428)#define GPIO3_DATAIN		(0xFFFBB42C)#define GPIO3_DATAOUT		(0xFFFBB430)#define GPIO3_DIRECTION		(0xFFFBB434)#define GPIO3_EDGE_CTRL1	(0xFFFBB438)#define GPIO3_EDGE_CTRL2	(0xFFFBB43C)#define GPIO3_CLEAR_IRQENABLE1	(0xFFFBB49C)#define GPIO3_CLEAR_IRQENABLE2	(0xFFFBB4A4)#define GPIO3_CLEAR_WAKEUPENA	(0xFFFBB4A8)#define GPIO3_CLEAR_DATAOUT	(0xFFFBB4B0)#define GPIO3_SET_IRQENABLE1	(0xFFFBB4DC)#define GPIO3_SET_IRQENABLE2	(0xFFFBB4E4)#define GPIO3_SET_WAKEUPENA	(0xFFFBB4E8)#define GPIO3_SET_DATAOUT	(0xFFFBB4F0)#define GPIO4_REVISION		(0xFFFBBC00)#define GPIO4_SYSCONFIG		(0xFFFBBC10)#define GPIO4_SYSSTATUS		(0xFFFBBC14)#define GPIO4_IRQSTATUS1	(0xFFFBBC18)#define GPIO4_IRQENABLE1	(0xFFFBBC1C)#define GPIO4_IRQSTATUS2	(0xFFFBBC20)#define GPIO4_IRQENABLE2	(0xFFFBBC24)#define GPIO4_WAKEUPENABLE	(0xFFFBBC28)#define GPIO4_DATAIN		(0xFFFBBC2C)#define GPIO4_DATAOUT		(0xFFFBBC30)#define GPIO4_DIRECTION		(0xFFFBBC34)#define GPIO4_EDGE_CTRL1	(0xFFFBBC38)#define GPIO4_EDGE_CTRL2	(0xFFFBBC3C)#define GPIO4_CLEAR_IRQENABLE1	(0xFFFBBC9C)#define GPIO4_CLEAR_IRQENABLE2	(0xFFFBBCA4)#define GPIO4_CLEAR_WAKEUPENA	(0xFFFBBCA8)#define GPIO4_CLEAR_DATAOUT	(0xFFFBBCB0)#define GPIO4_SET_IRQENABLE1	(0xFFFBBCDC)#define GPIO4_SET_IRQENABLE2	(0xFFFBBCE4)#define GPIO4_SET_WAKEUPENA	(0xFFFBBCE8)#define GPIO4_SET_DATAOUT	(0xFFFBBCF0)/********************************************* Clock and Power Management Registers********************************************//********************************************* UART Control Registers********************************************/#define UART1_RHR	(0xFFFB0000)#define UART1_THR	(0xFFFB0000)#define UART1_DLL	(0xFFFB0000)#define UART1_IER	(0xFFFB0004)#define UART1_DLH	(0xFFFB0004)#define UART1_IIR	(0xFFFB0008)#define UART1_FCR	(0xFFFB0008)#define UART1_EFR	(0xFFFB0008)#define UART1_LCR	(0xFFFB000C)#define UART1_MCR	(0xFFFB0010)#define UART1_XON1	(0xFFFB0010)#define UART1_LSR	(0xFFFB0014)#define UART1_XON2	(0xFFFB0014)#define UART1_MSR	(0xFFFB0018)#define UART1_TCR	(0xFFFB0018)#define UART1_XOFF1	(0xFFFB0018)#define UART1_SPR	(0xFFFB001C)#define UART1_TLR	(0xFFFB001C)#define UART1_XOFF2	(0xFFFB001C)#define UART1_MDR1	(0xFFFB0020)#define UART1_MDR2	(0xFFFB0024)#define UART1_SFLSR	(0xFFFB0028)#define UART1_TXFLL	(0xFFFB0028)#define UART1_RESUME	(0xFFFB002C)#define UART1_TXFLH	(0xFFFB002C)#define UART1_SFREGL	(0xFFFB0030)#define UART1_RXFLL	(0xFFFB0030)#define UART1_SFREGH	(0xFFFB0034)#define UART1_RXFLH	(0xFFFB0034)#define UART1_UASR	(0xFFFB0038)#define UART1_BLR	(0xFFFB0038)#define UART1_ACREG	(0xFFFB003C)#define UART1_SCR	(0xFFFB0040)#define UART1_SSR	(0xFFFB0044)#define UART1_EBLR	(0xFFFB0048)#define UART1_MVR	(0xFFFB0050)#define UART1_SYSC	(0xFFFB0054)#define UART1_SYSS	(0xFFFB0058)#define UART1_WER	(0xFFFB005C)#define UART2_RHR	(0xFFFB0800)#define UART2_THR	(0xFFFB0800)#define UART2_DLL	(0xFFFB0800)#define UART2_IER	(0xFFFB0804)#define UART2_DLH	(0xFFFB0804)#define UART2_IIR	(0xFFFB0808)#define UART2_FCR	(0xFFFB0808)#define UART2_EFR	(0xFFFB0808)#define UART2_LCR	(0xFFFB080C)#define UART2_MCR	(0xFFFB0810)#define UART2_XON1	(0xFFFB0810)#define UART2_LSR	(0xFFFB0814)#define UART2_XON2	(0xFFFB0814)#define UART2_MSR	(0xFFFB0818)#define UART2_TCR	(0xFFFB0818)#define UART2_XOFF1	(0xFFFB0818)#define UART2_SPR	(0xFFFB081C)#define UART2_TLR	(0xFFFB081C)#define UART2_XOFF2	(0xFFFB081C)#define UART2_MDR1	(0xFFFB0820)#define UART2_MDR2	(0xFFFB0824)#define UART2_SFLSR	(0xFFFB0828)#define UART2_TXFLL	(0xFFFB0828)#define UART2_RESUME	(0xFFFB082C)#define UART2_TXFLH	(0xFFFB082C)#define UART2_SFREGL	(0xFFFB0830)#define UART2_RXFLL	(0xFFFB0830)#define UART2_SFREGH	(0xFFFB0834)#define UART2_RXFLH	(0xFFFB0834)#define UART2_UASR	(0xFFFB0838)#define UART2_BLR	(0xFFFB0838)#define UART2_ACREG	(0xFFFB083C)#define UART2_SCR	(0xFFFB0840)#define UART2_SSR	(0xFFFB0844)#define UART2_EBLR	(0xFFFB0848)#define UART2_MVR	(0xFFFB0850)#define UART2_SYSC	(0xFFFB0854)#define UART2_SYSS	(0xFFFB0858)#define UART2_WER	(0xFFFB085C)/**************************************//* MPU Level 2 Interrupt Handler Registers *//**************************************/#define MPU_L2_ITR	(0xFFFE0000)#define MPU_L2_MIR	(0xFFFE0004) #define MPU_L2_SIR_IRQ	(0xFFFE0010)#define MPU_L2_SIR_FIQ	(0xFFFE0014)#define MPU_L2_CONTROL	(0xFFFE0018)#define MPU_L2_ILR0	(0xFFFE001C)#define MPU_L2_ILR1	(0xFFFE0020)#define MPU_L2_ILR2	(0xFFFE0024)#define MPU_L2_ILR3	(0xFFFE0028)#define MPU_L2_ILR4	(0xFFFE002C)#define MPU_L2_ILR5	(0xFFFE0030)#define MPU_L2_ILR6	(0xFFFE0034)#define MPU_L2_ILR7	(0xFFFE0038)#define MPU_L2_ILR8	(0xFFFE003C)#define MPU_L2_ILR9	(0xFFFE0040)#define MPU_L2_ILR10	(0xFFFE0044)#define MPU_L2_ILR11	(0xFFFE0048)#define MPU_L2_ILR12	(0xFFFE004C)#define MPU_L2_ILR13	(0xFFFE0050)#define MPU_L2_ILR14	(0xFFFE0054)#define MPU_L2_ILR15	(0xFFFE0058)#define MPU_L2_ILR16	(0xFFFE005C)#define MPU_L2_ILR17	(0xFFFE0060)#define MPU_L2_ILR18	(0xFFFE0064)#define MPU_L2_ILR19	(0xFFFE0068)#define MPU_L2_ILR20	(0xFFFE006C)#define MPU_L2_ILR21	(0xFFFE0070)#define MPU_L2_ILR22	(0xFFFE0074)#define MPU_L2_ILR23	(0xFFFE0078)#define MPU_L2_ILR24	(0xFFFE007C)#define MPU_L2_ILR25	(0xFFFE0080)#define MPU_L2_ILR26	(0xFFFE0084)#define MPU_L2_ILR27	(0xFFFE0088)#define MPU_L2_ILR28	(0xFFFE008C)#define MPU_L2_ILR29	(0xFFFE0090)#define MPU_L2_ILR30	(0xFFFE0094)#define MPU_L2_ILR31	(0xFFFE0098)#define MPU_L2_ISR	(0xFFFE009C)#define MPU_L2_STATUS	(0xFFFE00A0)#define MPU_L2_OCP_CFG	(0xFFFE00A4)#define MPU_L2_INTH_REV	(0xFFFE00A8)/*mpu l2 set2 */#define MPU_L2_ILR0_S1	(0xFFFE011C)#define MPU_L2_ILR1_S1	(0xFFFE0120)#define MPU_L2_ILR2_S1	(0xFFFE0124)#define MPU_L2_ILR3_S1	(0xFFFE0128)#define MPU_L2_ILR4_S1	(0xFFFE012C)#define MPU_L2_ILR5_S1	(0xFFFE0130)#define MPU_L2_ILR6_S1	(0xFFFE0134)#define MPU_L2_ILR7_S1	(0xFFFE0138)#define MPU_L2_ILR8_S1	(0xFFFE013C)#define MPU_L2_ILR9_S1	(0xFFFE0140)#define MPU_L2_ILR10_S1	(0xFFFE0144)#define MPU_L2_ILR11_S1	(0xFFFE0148)#define MPU_L2_ILR12_S1	(0xFFFE014C)#define MPU_L2_ILR13_S1	(0xFFFE0150)#define MPU_L2_ILR14_S1	(0xFFFE0154)#define MPU_L2_ILR15_S1	(0xFFFE0158)#define MPU_L2_ILR16_S1	(0xFFFE015C)#define MPU_L2_ILR17_S1	(0xFFFE0160)#define MPU_L2_ILR18_S1	(0xFFFE0164)#define MPU_L2_ILR19_S1	(0xFFFE0168)#define MPU_L2_ILR20_S1	(0xFFFE016C)#define MPU_L2_ILR21_S1	(0xFFFE0170)#define MPU_L2_ILR22_S1	(0xFFFE0174)#define MPU_L2_ILR23_S1	(0xFFFE0178)#define MPU_L2_ILR24_S1	(0xFFFE017C)#define MPU_L2_ILR25_S1	(0xFFFE0180)#define MPU_L2_ILR26_S1	(0xFFFE0184)#define MPU_L2_ILR27_S1	(0xFFFE0188)#define MPU_L2_ILR28_S1	(0xFFFE018C)#define MPU_L2_ILR29_S1	(0xFFFE0190)#define MPU_L2_ILR30_S1	(0xFFFE0194)#define MPU_L2_ILR31_S1	(0xFFFE0198)/*mpu l2 set3 */#define MPU_L2_ILR0_S2	(0xFFFE021C)#define MPU_L2_ILR1_S2	(0xFFFE0220)#define MPU_L2_ILR2_S2	(0xFFFE0224)#define MPU_L2_ILR3_S2	(0xFFFE0228)#define MPU_L2_ILR4_S2	(0xFFFE022C)#define MPU_L2_ILR5_S2	(0xFFFE0230)#define MPU_L2_ILR6_S2	(0xFFFE0234)#define MPU_L2_ILR7_S2	(0xFFFE0238)#define MPU_L2_ILR8_S2	(0xFFFE023C)#define MPU_L2_ILR9_S2	(0xFFFE0240)#define MPU_L2_ILR10_S2	(0xFFFE0244)#define MPU_L2_ILR11_S2	(0xFFFE0248)#define MPU_L2_ILR12_S2	(0xFFFE024C)#define MPU_L2_ILR13_S2	(0xFFFE0250)#define MPU_L2_ILR14_S2	(0xFFFE0254)#define MPU_L2_ILR15_S2	(0xFFFE0258)#define MPU_L2_ILR16_S2	(0xFFFE025C)#define MPU_L2_ILR17_S2	(0xFFFE0260)#define MPU_L2_ILR18_S2	(0xFFFE0264)#define MPU_L2_ILR19_S2	(0xFFFE0268)#define MPU_L2_ILR20_S2	(0xFFFE026C)#define MPU_L2_ILR21_S2	(0xFFFE0270)#define MPU_L2_ILR22_S2	(0xFFFE0274)#define MPU_L2_ILR23_S2	(0xFFFE0278)#define MPU_L2_ILR24_S2	(0xFFFE027C)#define MPU_L2_ILR25_S2	(0xFFFE0280)#define MPU_L2_ILR26_S2	(0xFFFE0284)#define MPU_L2_ILR27_S2	(0xFFFE0288)#define MPU_L2_ILR28_S2	(0xFFFE028C)#define MPU_L2_ILR29_S2	(0xFFFE0290)#define MPU_L2_ILR30_S2	(0xFFFE0294)#define MPU_L2_ILR31_S2	(0xFFFE0298)/*mpu l2 set4 */#define MPU_L2_ILR0_S3	(0xFFFE031C)#define MPU_L2_ILR1_S3	(0xFFFE0320)#define MPU_L2_ILR2_S3	(0xFFFE0324)#define MPU_L2_ILR3_S3	(0xFFFE0328)#define MPU_L2_ILR4_S3	(0xFFFE032C)#define MPU_L2_ILR5_S3	(0xFFFE0330)#define MPU_L2_ILR6_S3	(0xFFFE0334)#define MPU_L2_ILR7_S3	(0xFFFE0338)#define MPU_L2_ILR8_S3	(0xFFFE033C)#define MPU_L2_ILR9_S3	(0xFFFE0340)#define MPU_L2_ILR10_S3	(0xFFFE0344)#define MPU_L2_ILR11_S3	(0xFFFE0348)#define MPU_L2_ILR12_S3	(0xFFFE034C)#define MPU_L2_ILR13_S3	(0xFFFE0350)#define MPU_L2_ILR14_S3	(0xFFFE0354)#define MPU_L2_ILR15_S3	(0xFFFE0358)#define MPU_L2_ILR16_S3	(0xFFFE035C)#define MPU_L2_ILR17_S3	(0xFFFE0360)#define MPU_L2_ILR18_S3	(0xFFFE0364)#define MPU_L2_ILR19_S3	(0xFFFE0368)#define MPU_L2_ILR20_S3	(0xFFFE036C)#define MPU_L2_ILR21_S3	(0xFFFE0370)#define MPU_L2_ILR22_S3	(0xFFFE0374)#define MPU_L2_ILR23_S3	(0xFFFE0378)#define MPU_L2_ILR24_S3	(0xFFFE037C)#define MPU_L2_ILR25_S3	(0xFFFE0380)#define MPU_L2_ILR26_S3	(0xFFFE0384)#define MPU_L2_ILR27_S3	(0xFFFE0388)#define MPU_L2_ILR28_S3	(0xFFFE038C)#define MPU_L2_ILR29_S3	(0xFFFE0390)#define MPU_L2_ILR30_S3	(0xFFFE0394)#define MPU_L2_ILR31_S3	(0xFFFE0398)/**************************************//* MPU Level 1 Interrupt Handler Registers *//**************************************/#define MPU_L1_ITR	(0xFFFECB00)#define MPU_L1_MIR	(0xFFFECB04) #define MPU_L1_SIR_IRQ_CODE	(0xFFFECB10)#define MPU_L1_SIR_FIQ_CODE	(0xFFFECB14)#define MPU_L1_CONTROL	(0xFFFECB18)#define MPU_L1_ILR0	(0xFFFECB1C)#define MPU_L1_ILR1	(0xFFFECB20)#define MPU_L1_ILR2	(0xFFFECB24)#define MPU_L1_ILR3	(0xFFFECB28)#define MPU_L1_ILR4	(0xFFFECB2C)#define MPU_L1_ILR5	(0xFFFE0030)#define MPU_L1_ILR6	(0xFFFECB34)#define MPU_L1_ILR7	(0xFFFECB38)#define MPU_L1_ILR8	(0xFFFECB3C)#define MPU_L1_ILR9	(0xFFFECB40)#define MPU_L1_ILR10	(0xFFFECB44)#define MPU_L1_ILR11	(0xFFFECB48)#define MPU_L1_ILR12	(0xFFFECB4C)#define MPU_L1_ILR13	(0xFFFECB50)#define MPU_L1_ILR14	(0xFFFECB54)#define MPU_L1_ILR15	(0xFFFECB58)#define MPU_L1_ILR16	(0xFFFECB5C)#define MPU_L1_ILR17	(0xFFFECB60)
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