omap5912.h

skyeye for pxa270

/*
	omap5912.h - definitions of "omap5912" machine  for skyeye
	Copyright (C) 2004 Skyeye Develop Group
	for help please send mail to <[e-mail]>
	
	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the Free Software
	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
 
*/
/*
 * 02/25/2008  	initial version
 *
 *	 
 * */

#ifndef __OMAP5912_H_
#define __OMAP5912_H_
typedef enum omap_ioreg
{
	MPU_L2_ITR = 0xFFFE0000,
	MPU_L2_MIR = 0xFFFE0004,
	MPU_L2_SIR_IRQ = 0xFFFE0010,
	MPU_L2_SIR_FIQ = 0xFFFE0014,
	MPU_L2_CONTROL = 0xFFFE0018,
	MPU_L2_ILR0 = 0xFFFE001C,
	MPU_L2_ILR1 = 0xFFFE0020,
	MPU_L2_ILR2 = 0xFFFE0024,
	MPU_L2_ILR3 = 0xFFFE0028,
	MPU_L2_ILR4 = 0xFFFE002C,
	MPU_L2_ILR5 = 0xFFFE0030,
	MPU_L2_ILR6 = 0xFFFE0034,
	MPU_L2_ILR7 = 0xFFFE0038,
	MPU_L2_ILR8 = 0xFFFE003C,
	MPU_L2_ILR9 = 0xFFFE0040,
	MPU_L2_ILR10 = 0xFFFE0044,
	MPU_L2_ILR11 = 0xFFFE0048,
	MPU_L2_ILR12 = 0xFFFE004C,
	MPU_L2_ILR13 = 0xFFFE0050,
	MPU_L2_ILR14 = 0xFFFE0054,
	MPU_L2_ILR15 = 0xFFFE0058,
	MPU_L2_ILR16 = 0xFFFE005C,
	MPU_L2_ILR17 = 0xFFFE0060,
	MPU_L2_ILR18 = 0xFFFE0064,
	MPU_L2_ILR19 = 0xFFFE0068,
	MPU_L2_ILR20 = 0xFFFE006C,
	MPU_L2_ILR21 = 0xFFFE0070,
	MPU_L2_ILR22 = 0xFFFE0074,
	MPU_L2_ILR23 = 0xFFFE0078,
	MPU_L2_ILR24 = 0xFFFE007C,
	MPU_L2_ILR25 = 0xFFFE0080,
	MPU_L2_ILR26 = 0xFFFE0084,
	MPU_L2_ILR27 = 0xFFFE0088,
	MPU_L2_ILR28 = 0xFFFE008C,
	MPU_L2_ILR29 = 0xFFFE0090,
	MPU_L2_ILR30 = 0xFFFE0094,
	MPU_L2_ILR31 = 0xFFFE0098,

	MPU_L2_ISR = 0xFFFE009C,
	MPU_L2_STATUS = 0xFFFE00A0,
	MPU_L2_OCP_CFG = 0xFFFE00A4,
	MPU_L2_INTH_REV = 0xFFFE00A8,


	MPU_L2_ITR_S1 = 0xFFFE0100,
	MPU_L2_MIR_S1 = 0xFFFE0104,
	MPU_L2_SIR_IRQ_S1 = 0xFFFE0110,
	MPU_L2_SIR_FIQ_S1 = 0xFFFE0114,
	MPU_L2_CONTROL_S1 = 0xFFFE0118,
MPU_L2_ILR0_S1	=0xFFFE011C,
MPU_L2_ILR1_S1	=0xFFFE0120,
MPU_L2_ILR2_S1	=0xFFFE0124,
MPU_L2_ILR3_S1	=0xFFFE0128,
MPU_L2_ILR4_S1	=0xFFFE012C,
MPU_L2_ILR5_S1	=0xFFFE0130,
MPU_L2_ILR6_S1	=0xFFFE0134,
MPU_L2_ILR7_S1	=0xFFFE0138,
MPU_L2_ILR8_S1	=0xFFFE013C,
MPU_L2_ILR9_S1	=0xFFFE0140,
MPU_L2_ILR10_S1	=0xFFFE0144,
MPU_L2_ILR11_S1	=0xFFFE0148,
MPU_L2_ILR12_S1	=0xFFFE014C,
MPU_L2_ILR13_S1	=0xFFFE0150,
MPU_L2_ILR14_S1	=0xFFFE0154,
MPU_L2_ILR15_S1	=0xFFFE0158,
MPU_L2_ILR16_S1	=0xFFFE015C,
MPU_L2_ILR17_S1	=0xFFFE0160,
MPU_L2_ILR18_S1	=0xFFFE0164,
MPU_L2_ILR19_S1	=0xFFFE0168,
MPU_L2_ILR20_S1	=0xFFFE016C,
MPU_L2_ILR21_S1	=0xFFFE0170,
MPU_L2_ILR22_S1	=0xFFFE0174,
MPU_L2_ILR23_S1	=0xFFFE0178,
MPU_L2_ILR24_S1	=0xFFFE017C,
MPU_L2_ILR25_S1	=0xFFFE0180,
MPU_L2_ILR26_S1	=0xFFFE0184,
MPU_L2_ILR27_S1	=0xFFFE0188,
MPU_L2_ILR28_S1	=0xFFFE018C,
MPU_L2_ILR29_S1	=0xFFFE0190,
MPU_L2_ILR30_S1	=0xFFFE0194,
MPU_L2_ILR31_S1	=0xFFFE0198,
/*mpu l2 set3 */

	MPU_L2_ITR_S2 = 0xFFFE0200,
	MPU_L2_MIR_S2 = 0xFFFE0204,
	MPU_L2_SIR_IRQ_S2 = 0xFFFE0210,
	MPU_L2_SIR_FIQ_S2 = 0xFFFE0214,
	MPU_L2_CONTROL_S2 = 0xFFFE0218,
MPU_L2_ILR0_S2	=0xFFFE021C,
MPU_L2_ILR1_S2	=0xFFFE0220,
MPU_L2_ILR2_S2	=0xFFFE0224,
MPU_L2_ILR3_S2	=0xFFFE0228,
MPU_L2_ILR4_S2	=0xFFFE022C,
MPU_L2_ILR5_S2	=0xFFFE0230,
MPU_L2_ILR6_S2	=0xFFFE0234,
MPU_L2_ILR7_S2	=0xFFFE0238,
MPU_L2_ILR8_S2	=0xFFFE023C,
MPU_L2_ILR9_S2	=0xFFFE0240,
MPU_L2_ILR10_S2	=0xFFFE0244,
MPU_L2_ILR11_S2	=0xFFFE0248,
MPU_L2_ILR12_S2	=0xFFFE024C,
MPU_L2_ILR13_S2	=0xFFFE0250,
MPU_L2_ILR14_S2	=0xFFFE0254,
MPU_L2_ILR15_S2	=0xFFFE0258,
MPU_L2_ILR16_S2	=0xFFFE025C,
MPU_L2_ILR17_S2	=0xFFFE0260,
MPU_L2_ILR18_S2	=0xFFFE0264,
MPU_L2_ILR19_S2	=0xFFFE0268,
MPU_L2_ILR20_S2	=0xFFFE026C,
MPU_L2_ILR21_S2	=0xFFFE0270,
MPU_L2_ILR22_S2	=0xFFFE0274,
MPU_L2_ILR23_S2	=0xFFFE0278,
MPU_L2_ILR24_S2	=0xFFFE027C,
MPU_L2_ILR25_S2	=0xFFFE0280,
MPU_L2_ILR26_S2	=0xFFFE0284,
MPU_L2_ILR27_S2	=0xFFFE0288,
MPU_L2_ILR28_S2	=0xFFFE028C,
MPU_L2_ILR29_S2	=0xFFFE0290,
MPU_L2_ILR30_S2	=0xFFFE0294,
MPU_L2_ILR31_S2	=0xFFFE0298,

/*mpu l2 set4 */
	MPU_L2_ITR_S3 = 0xFFFE0300,
	MPU_L2_MIR_S3 = 0xFFFE0304,
	MPU_L2_SIR_IRQ_S3 = 0xFFFE0310,
	MPU_L2_SIR_FIQ_S3 = 0xFFFE0314,
	MPU_L2_CONTROL_S3 = 0xFFFE0318,
MPU_L2_ILR0_S3	=0xFFFE031C,
MPU_L2_ILR1_S3	=0xFFFE0320,
MPU_L2_ILR2_S3	=0xFFFE0324,
MPU_L2_ILR3_S3	=0xFFFE0328,
MPU_L2_ILR4_S3	=0xFFFE032C,
MPU_L2_ILR5_S3	=0xFFFE0330,
MPU_L2_ILR6_S3	=0xFFFE0334,
MPU_L2_ILR7_S3	=0xFFFE0338,
MPU_L2_ILR8_S3	=0xFFFE033C,
MPU_L2_ILR9_S3	=0xFFFE0340,
MPU_L2_ILR10_S3	=0xFFFE0344,
MPU_L2_ILR11_S3	=0xFFFE0348,
MPU_L2_ILR12_S3	=0xFFFE034C,
MPU_L2_ILR13_S3	=0xFFFE0350,
MPU_L2_ILR14_S3	=0xFFFE0354,
MPU_L2_ILR15_S3	=0xFFFE0358,
MPU_L2_ILR16_S3	=0xFFFE035C,
MPU_L2_ILR17_S3	=0xFFFE0360,
MPU_L2_ILR18_S3	=0xFFFE0364,
MPU_L2_ILR19_S3	=0xFFFE0368,
MPU_L2_ILR20_S3	=0xFFFE036C,
MPU_L2_ILR21_S3	=0xFFFE0370,
MPU_L2_ILR22_S3	=0xFFFE0374,
MPU_L2_ILR23_S3	=0xFFFE0378,
MPU_L2_ILR24_S3	=0xFFFE037C,
MPU_L2_ILR25_S3	=0xFFFE0380,
MPU_L2_ILR26_S3	=0xFFFE0384,
MPU_L2_ILR27_S3	=0xFFFE0388,
MPU_L2_ILR28_S3	=0xFFFE038C,
MPU_L2_ILR29_S3	=0xFFFE0390,
MPU_L2_ILR30_S3	=0xFFFE0394,
MPU_L2_ILR31_S3	=0xFFFE0398,

	/*interrupt level 1*/
	MPU_L1_ITR = 0xFFFECB00,
	MPU_L1_MIR = 0xFFFECB04,
	MPU_L1_SIR_IRQ_CODE = 0xFFFECB10,
	MPU_L1_SIR_FIQ_CODE = 0xFFFECB14,
	MPU_L1_CONTROL = 0xFFFECB18,
	MPU_L1_ILR0 = 0xFFFECB1C,
	MPU_L1_ILR1 = 0xFFFECB20,
	MPU_L1_ILR2 = 0xFFFECB24,
	MPU_L1_ILR3 = 0xFFFECB28,
	MPU_L1_ILR4 = 0xFFFECB2C,
	MPU_L1_ILR5 = 0xFFFE0030,
	MPU_L1_ILR6 = 0xFFFECB34,
	MPU_L1_ILR7 = 0xFFFECB38,
	MPU_L1_ILR8 = 0xFFFECB3C,
	MPU_L1_ILR9 = 0xFFFECB40,
	MPU_L1_ILR10 = 0xFFFECB44,
	MPU_L1_ILR11 = 0xFFFECB48,
	MPU_L1_ILR12 = 0xFFFECB4C,
	MPU_L1_ILR13 = 0xFFFECB50,
	MPU_L1_ILR14 = 0xFFFECB54,
	MPU_L1_ILR15 = 0xFFFECB58,
	MPU_L1_ILR16 = 0xFFFECB5C,
	MPU_L1_ILR17 = 0xFFFECB60,
	MPU_L1_ILR18 = 0xFFFECB64,
	MPU_L1_ILR19 = 0xFFFECB68,
	MPU_L1_ILR20 = 0xFFFECB6C,
	MPU_L1_ILR21 = 0xFFFECB70,
	MPU_L1_ILR22 = 0xFFFECB74,
	MPU_L1_ILR23 = 0xFFFECB78,
	MPU_L1_ILR24 = 0xFFFECB7C,
	MPU_L1_ILR25 = 0xFFFECB80,
	MPU_L1_ILR26 = 0xFFFECB84,
	MPU_L1_ILR27 = 0xFFFECB88,
	MPU_L1_ILR28 = 0xFFFECB8C,
	MPU_L1_ILR29 = 0xFFFECB90,
	MPU_L1_ILR30 = 0xFFFECB94,
	MPU_L1_ILR31 = 0xFFFECB98,
	MPU_L1_ISR = 0xFFFECB9C,
	MPU_L1_ENHANCEED_CNTL = 0xFFFECBA0,
	/** gpio register*/
	GPIO1_REVISION	= 0xFFFBE400,
	GPIO1_SYSCONFIG	= 0xFFFBE410,
	GPIO1_SYSSTATUS	= 0xFFFBE414,
	GPIO1_IRQSTATUS1 = 0xFFFBE418,
	GPIO1_IRQENABLE1 = 0xFFFBE41C,
	GPIO1_IRQSTATUS2 = 0xFFFBE420,
	GPIO1_IRQENABLE2 = 0xFFFBE424,
	GPIO1_WAKEUPENABLE = 0xFFFBE428,
	GPIO1_DATAIN	= 0xFFFBE42C,
	GPIO1_DATAOUT	= 0xFFFBE430,
	GPIO1_DIRECTION	= 0xFFFBE434,
	GPIO1_EDGE_CTRL1 = 0xFFFBE438,
	GPIO1_EDGE_CTRL2 = 0xFFFBE43C,
	GPIO1_CLEAR_IRQENABLE1 = 0xFFFBE49C,
	GPIO1_CLEAR_IRQENABLE2 = 0xFFFBE4A4,
	GPIO1_CLEAR_WAKEUPENA = 0xFFFBE4A8,
	GPIO1_CLEAR_DATAOUT = 0xFFFBE4B0,
	GPIO1_SET_IRQENABLE1 = 0xFFFBE4DC,
	GPIO1_SET_IRQENABLE2 = 0xFFFBE4E4,
	GPIO1_SET_WAKEUPENA = 0xFFFBE4E8,
	GPIO1_SET_DATAOUT = 0xFFFBE4F0,

	GPIO2_REVISION	= 0xFFFBEC00,
	GPIO2_SYSCONFIG	= 0xFFFBEC10,
	GPIO2_SYSSTATUS	= 0xFFFBEC14,
	GPIO2_IRQSTATUS1 = 0xFFFBEC18,
	GPIO2_IRQENABLE1 = 0xFFFBEC1C,
	GPIO2_IRQSTATUS2 = 0xFFFBEC20,
	GPIO2_IRQENABLE2 = 0xFFFBEC24,
	GPIO2_WAKEUPENABLE = 0xFFFBEC28,
	GPIO2_DATAIN	= 0xFFFBEC2C,
	GPIO2_DATAOUT	= 0xFFFBEC30,
	GPIO2_DIRECTION	= 0xFFFBEC34,
	GPIO2_EDGE_CTRL1 = 0xFFFBEC38,
	GPIO2_EDGE_CTRL2 = 0xFFFBEC3C,
	GPIO2_CLEAR_IRQENABLE1 = 0xFFFBEC9C,
	GPIO2_CLEAR_IRQENABLE2 = 0xFFFBECA4,
	GPIO2_CLEAR_WAKEUPENA = 0xFFFBECA8,
	GPIO2_CLEAR_DATAOUT = 0xFFFBECB0,
	GPIO2_SET_IRQENABLE1 = 0xFFFBECDC,
	GPIO2_SET_IRQENABLE2 = 0xFFFBECE4,
	GPIO2_SET_WAKEUPENA = 0xFFFBECE8,
	GPIO2_SET_DATAOUT = 0xFFFBECF0,

	GPIO3_REVISION	= 0xFFFBB400,
	GPIO3_SYSCONFIG	= 0xFFFBB410,
	GPIO3_SYSSTATUS	= 0xFFFBB414,
	GPIO3_IRQSTATUS1 = 0xFFFBB418,
	GPIO3_IRQENABLE1 = 0xFFFBB41C,
	GPIO3_IRQSTATUS2 = 0xFFFBB420,
	GPIO3_IRQENABLE2 = 0xFFFBB424,
	GPIO3_WAKEUPENABLE = 0xFFFBB428,
	GPIO3_DATAIN	= 0xFFFBB42C,
	GPIO3_DATAOUT	= 0xFFFBB430,
	GPIO3_DIRECTION	= 0xFFFBB434,
	GPIO3_EDGE_CTRL1 = 0xFFFBB438,
	GPIO3_EDGE_CTRL2 = 0xFFFBB43C,
	GPIO3_CLEAR_IRQENABLE1 = 0xFFFBB49C,
	GPIO3_CLEAR_IRQENABLE2 = 0xFFFBB4A4,
	GPIO3_CLEAR_WAKEUPENA = 0xFFFBB4A8,
	GPIO3_CLEAR_DATAOUT = 0xFFFBB4B0,
	GPIO3_SET_IRQENABLE1 = 0xFFFBB4DC,
	GPIO3_SET_IRQENABLE2 = 0xFFFBB4E4,
	GPIO3_SET_WAKEUPENA = 0xFFFBB4E8,
	GPIO3_SET_DATAOUT = 0xFFFBB4F0,

	GPIO4_REVISION	= 0xFFFBBC00,
	GPIO4_SYSCONFIG	= 0xFFFBBC10,
	GPIO4_SYSTATUS	= 0xFFFBBC14,
	GPIO4_IRQSTATUS1 = 0xFFFBBC18,
	GPIO4_IRQENABLE1 = 0xFFFBBC1C,
	GPIO4_IRQSTATUS2 = 0xFFFBBC20,
	GPIO4_IRQENABLE2 = 0xFFFBBC24,
	GPIO4_WAKEUPENABLE = 0xFFFBBC28,
	GPIO4_DATAIN	= 0xFFFBBC2C,
	GPIO4_DATAOUT	= 0xFFFBBC30,
	GPIO4_DIRECTION	= 0xFFFBBC34,
	GPIO4_EDGE_CTRL1 = 0xFFFBBC38,
	GPIO4_EDGE_CTRL2 = 0xFFFBBC3C,
	GPIO4_CLEAR_IRQENABLE1 = 0xFFFBBC9C,
	GPIO4_CLEAR_IRQENABLE2 = 0xFFFBBCA4,
	GPIO4_CLEAR_WAKEUPENA = 0xFFFBBCA8,
	GPIO4_CLEAR_DATAOUT = 0xFFFBBCB0,
	GPIO4_SET_IRQENABLE1 = 0xFFFBBCDC,
	GPIO4_SET_IRQENABLE2 = 0xFFFBBCE4,
	GPIO4_SET_WAKEUPENA = 0xFFFBBCE8,
	GPIO4_SET_DATAOUT = 0xFFFBBCF0,


	/* os timer register*/
	OS_TIMER_TICK_VAL = 0xFFFB9000,
	OS_TIMER_TICK_CNTR = 0xFFFB9004,
	OS_TIMER_CTRL = 0xFFFB9008,
	
	/**mpu timer*/
	MPU_CNTL_TIMER1 = 0xFFFEC500,
	MPU_LOAD_TIMER1 = 0xFFFEC504,
	MPU_READ_TIMER1 = 0xFFFEC508,

	MPU_CNTL_TIMER2 = 0xFFFEC600,
	MPU_LOAD_TIMER2 = 0xFFFEC604,
	MPU_READ_TIMER2 = 0xFFFEC608,

	MPU_CNTL_TIMER3 = 0xFFFEC700,
	MPU_LOAD_TIMER3 = 0xFFFEC704,
	MPU_READ_TIMER3 = 0xFFFEC708,
	
	/* syncronized timer 32k read 16bit*/
	TIMER_32K_SYNCHRONIZED = 0xFFFBC410,

	/** uart register*/	

	UART1_THR = 0xFFFB0000,
	UART1_IIR = 0xFFFB0008,
	UART1_LSR = 0xFFFB0014,
#if 0
	UART1_RHR = 0xFFFB0000,
	UART1_THR = 0xFFFB0000,
	UART1_DLL = 0xFFFB0000,
	UART1_IER = 0xFFFB0004,
	UART1_DLH = 0xFFFB0004,
	UART1_IIR = 0xFFFB0008,
	UART1_FCR = 0xFFFB0008,
	UART1_EFR = 0xFFFB0008,
	UART1_LCR = 0xFFFB000C,
	UART1_MCR = 0xFFFB0010,
	UART1_XON1 = 0xFFFB0010,
	UART1_LSR = 0xFFFB0014,
	UART1_XON2 = 0xFFFB0014,
	UART1_MSR = 0xFFFB0018,
	UART1_TCR = 0xFFFB0018,
	UART1_XOFF1 = 0xFFFB0018,
	UART1_SPR = 0xFFFB001C,
	UART1_TLR = 0xFFFB001C,
	UART1_XOFF2 = 0xFFFB001C,
	UART1_MDR1 = 0xFFFB0020,
	UART1_MDR2 = 0xFFFB0024,
	UART1_SFLSR = 0xFFFB0028,
	UART1_TXFLL = 0xFFFB0028,
	UART1_RESUME = 0xFFFB002C,
	UART1_TXFLH = 0xFFFB002C,
	UART1_SFREGL = 0xFFFB0030,
	UART1_RXFLL = 0xFFFB0030,
	UART1_SFREGH = 0xFFFB0034,
	UART1_RXFLH = 0xFFFB0034,
	UART1_UASR = 0xFFFB0038,
	UART1_BLR = 0xFFFB0038,
	UART1_ACREG = 0xFFFB003C,
	UART1_SCR = 0xFFFB0040,
	UART1_SSR = 0xFFFB0044,
	UART1_EBLR = 0xFFFB0048,
	UART1_MVR = 0xFFFB0050,
	UART1_SYSC = 0xFFFB0054,
	UART1_SYSS = 0xFFFB0058,
	UART1_WER = 0xFFFB005C,
#endif