au1000.h

skyeye for pxa270

#define	AU1100_LCD_INT            30
#define AU1000_AC97C_INT          31
#define AU1000_GPIO_0             32
#define AU1000_GPIO_1             33
#define AU1000_GPIO_2             34
#define AU1000_GPIO_3             35
#define AU1000_GPIO_4             36
#define AU1000_GPIO_5             37
#define AU1000_GPIO_6             38
#define AU1000_GPIO_7             39
#define AU1000_GPIO_8             40
#define AU1000_GPIO_9             41
#define AU1000_GPIO_10            42
#define AU1000_GPIO_11            43
#define AU1000_GPIO_12            44
#define AU1000_GPIO_13            45
#define AU1000_GPIO_14            46
#define AU1000_GPIO_15            47
#define AU1000_GPIO_16            48
#define AU1000_GPIO_17            49
#define AU1000_GPIO_18            50
#define AU1000_GPIO_19            51
#define AU1000_GPIO_20            52
#define AU1000_GPIO_21            53
#define AU1000_GPIO_22            54
#define AU1000_GPIO_23            55
#define AU1000_GPIO_24            56
#define AU1000_GPIO_25            57
#define AU1000_GPIO_26            58
#define AU1000_GPIO_27            59
#define AU1000_GPIO_28            60
#define AU1000_GPIO_29            61
#define AU1000_GPIO_30            62
#define AU1000_GPIO_31            63

#define UART0_ADDR                0xB1100000
#define UART1_ADDR                0xB1200000
#define UART3_ADDR                0xB1400000

#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
#define USB_HOST_CONFIG           0xB017fffc

#define AU1100_ETH0_BASE	  0xB0500000
#define AU1100_MAC0_ENABLE       0xB0520000
#define NUM_ETH_INTERFACES 1
#endif /* CONFIG_SOC_AU1100 */

#ifdef CONFIG_SOC_AU1550
#define AU1550_UART0_INT          0
#define AU1550_PCI_INTA           1
#define AU1550_PCI_INTB           2
#define AU1550_DDMA_INT           3
#define AU1550_CRYPTO_INT         4
#define AU1550_PCI_INTC           5
#define AU1550_PCI_INTD           6
#define AU1550_PCI_RST_INT        7
#define AU1550_UART1_INT          8
#define AU1550_UART3_INT          9
#define AU1550_PSC0_INT           10
#define AU1550_PSC1_INT           11
#define AU1550_PSC2_INT           12
#define AU1550_PSC3_INT           13
#define AU1000_TOY_INT			  14
#define AU1000_TOY_MATCH0_INT     15
#define AU1000_TOY_MATCH1_INT     16
#define AU1000_TOY_MATCH2_INT     17
#define AU1000_RTC_INT            18
#define AU1000_RTC_MATCH0_INT     19
#define AU1000_RTC_MATCH1_INT     20
#define AU1000_RTC_MATCH2_INT     21
#define AU1550_NAND_INT           23
#define AU1550_USB_DEV_REQ_INT    24
#define AU1550_USB_DEV_SUS_INT    25
#define AU1550_USB_HOST_INT       26
#define AU1000_USB_DEV_REQ_INT    AU1550_USB_DEV_REQ_INT
#define AU1000_USB_DEV_SUS_INT    AU1550_USB_DEV_SUS_INT
#define AU1000_USB_HOST_INT       AU1550_USB_HOST_INT
#define AU1550_MAC0_DMA_INT       27
#define AU1550_MAC1_DMA_INT       28
#define AU1000_GPIO_0             32
#define AU1000_GPIO_1             33
#define AU1000_GPIO_2             34
#define AU1000_GPIO_3             35
#define AU1000_GPIO_4             36
#define AU1000_GPIO_5             37
#define AU1000_GPIO_6             38
#define AU1000_GPIO_7             39
#define AU1000_GPIO_8             40
#define AU1000_GPIO_9             41
#define AU1000_GPIO_10            42
#define AU1000_GPIO_11            43
#define AU1000_GPIO_12            44
#define AU1000_GPIO_13            45
#define AU1000_GPIO_14            46
#define AU1000_GPIO_15            47
#define AU1550_GPIO_200           48
#define AU1500_GPIO_201_205       49	// Logical or of GPIO201:205
#define AU1500_GPIO_16            50
#define AU1500_GPIO_17            51
#define AU1500_GPIO_20            52
#define AU1500_GPIO_21            53
#define AU1500_GPIO_22            54
#define AU1500_GPIO_23            55
#define AU1500_GPIO_24            56
#define AU1500_GPIO_25            57
#define AU1500_GPIO_26            58
#define AU1500_GPIO_27            59
#define AU1500_GPIO_28            60
#define AU1500_GPIO_206           61
#define AU1500_GPIO_207           62
#define AU1500_GPIO_208_218       63	// Logical or of GPIO208:218

/* shortcuts */
#define INTA AU1550_PCI_INTA
#define INTB AU1550_PCI_INTB
#define INTC AU1550_PCI_INTC
#define INTD AU1550_PCI_INTD

#define UART0_ADDR                0xB1100000
#define UART1_ADDR                0xB1200000
#define UART3_ADDR                0xB1400000

#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
#define USB_OHCI_LEN              0x00060000
#define USB_HOST_CONFIG           0xB4027ffc

#define AU1550_ETH0_BASE      0xB0500000
#define AU1550_ETH1_BASE      0xB0510000
#define AU1550_MAC0_ENABLE       0xB0520000
#define AU1550_MAC1_ENABLE       0xB0520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1550 */

#ifdef CONFIG_SOC_AU1200
#define AU1200_UART0_INT          0
#define AU1200_SWT_INT            1
#define AU1200_SD_INT             2
#define AU1200_DDMA_INT           3
#define AU1200_MAE_BE_INT         4
#define AU1200_GPIO_200           5
#define AU1200_GPIO_201           6
#define AU1200_GPIO_202           7
#define AU1200_UART1_INT          8
#define AU1200_MAE_FE_INT         9
#define AU1200_PSC0_INT           10
#define AU1200_PSC1_INT           11
#define AU1200_AES_INT            12
#define AU1200_CAMERA_INT         13
#define AU1000_TOY_INT			  14
#define AU1000_TOY_MATCH0_INT     15
#define AU1000_TOY_MATCH1_INT     16
#define AU1000_TOY_MATCH2_INT     17
#define AU1000_RTC_INT            18
#define AU1000_RTC_MATCH0_INT     19
#define AU1000_RTC_MATCH1_INT     20
#define AU1000_RTC_MATCH2_INT     21
#define AU1200_NAND_INT           23
#define AU1200_GPIO_204           24
#define AU1200_GPIO_205           25
#define AU1200_GPIO_206           26
#define AU1200_GPIO_207           27
#define AU1200_GPIO_208_215       28 // Logical OR of 208:215
#define AU1200_USB_INT            29
#define AU1000_USB_HOST_INT		  AU1200_USB_INT
#define AU1200_LCD_INT            30
#define AU1200_MAE_BOTH_INT       31
#define AU1000_GPIO_0             32
#define AU1000_GPIO_1             33
#define AU1000_GPIO_2             34
#define AU1000_GPIO_3             35
#define AU1000_GPIO_4             36
#define AU1000_GPIO_5             37
#define AU1000_GPIO_6             38
#define AU1000_GPIO_7             39
#define AU1000_GPIO_8             40
#define AU1000_GPIO_9             41
#define AU1000_GPIO_10            42
#define AU1000_GPIO_11            43
#define AU1000_GPIO_12            44
#define AU1000_GPIO_13            45
#define AU1000_GPIO_14            46
#define AU1000_GPIO_15            47
#define AU1000_GPIO_16            48
#define AU1000_GPIO_17            49
#define AU1000_GPIO_18            50
#define AU1000_GPIO_19            51
#define AU1000_GPIO_20            52
#define AU1000_GPIO_21            53
#define AU1000_GPIO_22            54
#define AU1000_GPIO_23            55
#define AU1000_GPIO_24            56
#define AU1000_GPIO_25            57
#define AU1000_GPIO_26            58
#define AU1000_GPIO_27            59
#define AU1000_GPIO_28            60
#define AU1000_GPIO_29            61
#define AU1000_GPIO_30            62
#define AU1000_GPIO_31            63

#define UART0_ADDR                0xB1100000
#define UART1_ADDR                0xB1200000

#define USB_UOC_BASE              0x14020020
#define USB_UOC_LEN               0x20
#define USB_OHCI_BASE             0x14020100
#define USB_OHCI_LEN              0x100
#define USB_EHCI_BASE             0x14020200
#define USB_EHCI_LEN              0x100
#define USB_UDC_BASE              0x14022000
#define USB_UDC_LEN               0x2000
#define USB_MSR_BASE			  0xB4020000
#define USB_MSR_MCFG              4
#define USBMSRMCFG_OMEMEN         0
#define USBMSRMCFG_OBMEN          1
#define USBMSRMCFG_EMEMEN         2
#define USBMSRMCFG_EBMEN          3
#define USBMSRMCFG_DMEMEN         4
#define USBMSRMCFG_DBMEN          5
#define USBMSRMCFG_GMEMEN         6
#define USBMSRMCFG_OHCCLKEN       16
#define USBMSRMCFG_EHCCLKEN       17
#define USBMSRMCFG_UDCCLKEN       18
#define USBMSRMCFG_PHYPLLEN       19
#define USBMSRMCFG_RDCOMB         30
#define USBMSRMCFG_PFEN           31

#endif /* CONFIG_SOC_AU1200 */

#define AU1000_LAST_INTC0_INT     31
#define AU1000_LAST_INTC1_INT     63
#define AU1000_MAX_INTR           63
#define INTX    		0xFF /* not valid */

/* Programmable Counters 0 and 1 */
#define SYS_BASE                   0xB1900000
#define SYS_COUNTER_CNTRL          (SYS_BASE + 0x14)
  #define SYS_CNTRL_E1S            (1<<23)
  #define SYS_CNTRL_T1S            (1<<20)
  #define SYS_CNTRL_M21            (1<<19)
  #define SYS_CNTRL_M11            (1<<18)
  #define SYS_CNTRL_M01            (1<<17)
  #define SYS_CNTRL_C1S            (1<<16)
  #define SYS_CNTRL_BP             (1<<14)
  #define SYS_CNTRL_EN1            (1<<13)
  #define SYS_CNTRL_BT1            (1<<12)
  #define SYS_CNTRL_EN0            (1<<11)
  #define SYS_CNTRL_BT0            (1<<10)
  #define SYS_CNTRL_E0             (1<<8)
  #define SYS_CNTRL_E0S            (1<<7)
  #define SYS_CNTRL_32S            (1<<5)
  #define SYS_CNTRL_T0S            (1<<4)
  #define SYS_CNTRL_M20            (1<<3)
  #define SYS_CNTRL_M10            (1<<2)
  #define SYS_CNTRL_M00            (1<<1)
  #define SYS_CNTRL_C0S            (1<<0)

/* Programmable Counter 0 Registers */
#define SYS_TOYTRIM                 (SYS_BASE + 0)
#define SYS_TOYWRITE                (SYS_BASE + 4)
#define SYS_TOYMATCH0               (SYS_BASE + 8)
#define SYS_TOYMATCH1               (SYS_BASE + 0xC)
#define SYS_TOYMATCH2               (SYS_BASE + 0x10)
#define SYS_TOYREAD                 (SYS_BASE + 0x40)

/* Programmable Counter 1 Registers */
#define SYS_RTCTRIM                 (SYS_BASE + 0x44)
#define SYS_RTCWRITE                (SYS_BASE + 0x48)
#define SYS_RTCMATCH0               (SYS_BASE + 0x4C)
#define SYS_RTCMATCH1               (SYS_BASE + 0x50)
#define SYS_RTCMATCH2               (SYS_BASE + 0x54)
#define SYS_RTCREAD                 (SYS_BASE + 0x58)

/* I2S Controller */
#define I2S_DATA                    0xB1000000
  #define I2S_DATA_MASK        (0xffffff)
#define I2S_CONFIG                0xB1000004
  #define I2S_CONFIG_XU        (1<<25)
  #define I2S_CONFIG_XO        (1<<24)
  #define I2S_CONFIG_RU        (1<<23)
  #define I2S_CONFIG_RO        (1<<22)
  #define I2S_CONFIG_TR        (1<<21)
  #define I2S_CONFIG_TE        (1<<20)
  #define I2S_CONFIG_TF        (1<<19)
  #define I2S_CONFIG_RR        (1<<18)
  #define I2S_CONFIG_RE        (1<<17)
  #define I2S_CONFIG_RF        (1<<16)
  #define I2S_CONFIG_PD        (1<<11)
  #define I2S_CONFIG_LB        (1<<10)
  #define I2S_CONFIG_IC        (1<<9)
  #define I2S_CONFIG_FM_BIT    7
  #define I2S_CONFIG_FM_MASK     (0x3 << I2S_CONFIG_FM_BIT)
    #define I2S_CONFIG_FM_I2S    (0x0 << I2S_CONFIG_FM_BIT)
    #define I2S_CONFIG_FM_LJ     (0x1 << I2S_CONFIG_FM_BIT)
    #define I2S_CONFIG_FM_RJ     (0x2 << I2S_CONFIG_FM_BIT)
  #define I2S_CONFIG_TN        (1<<6)
  #define I2S_CONFIG_RN        (1<<5)
  #define I2S_CONFIG_SZ_BIT    0
  #define I2S_CONFIG_SZ_MASK     (0x1F << I2S_CONFIG_SZ_BIT)

#define I2S_CONTROL                0xB1000008
  #define I2S_CONTROL_D         (1<<1)
  #define I2S_CONTROL_CE        (1<<0)

/* USB Host Controller */
#ifndef USB_OHCI_LEN
#define USB_OHCI_LEN              0x00100000
#endif

#ifndef CONFIG_SOC_AU1200

/* USB Device Controller */
#define USBD_EP0RD                0xB0200000
#define USBD_EP0WR                0xB0200004
#define USBD_EP2WR                0xB0200008
#define USBD_EP3WR                0xB020000C
#define USBD_EP4RD                0xB0200010
#define USBD_EP5RD                0xB0200014
#define USBD_INTEN                0xB0200018
#define USBD_INTSTAT              0xB020001C
  #define USBDEV_INT_SOF       (1<<12)
  #define USBDEV_INT_HF_BIT    6
  #define USBDEV_INT_HF_MASK   (0x3f << USBDEV_INT_HF_BIT)
  #define USBDEV_INT_CMPLT_BIT  0
  #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
#define USBD_CONFIG               0xB0200020
#define USBD_EP0CS                0xB0200024
#define USBD_EP2CS                0xB0200028
#define USBD_EP3CS                0xB020002C
#define USBD_EP4CS                0xB0200030
#define USBD_EP5CS                0xB0200034
  #define USBDEV_CS_SU         (1<<14)
  #define USBDEV_CS_NAK        (1<<13)
  #define USBDEV_CS_ACK        (1<<12)
  #define USBDEV_CS_BUSY       (1<<11)
  #define USBDEV_CS_TSIZE_BIT  1
  #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
  #define USBDEV_CS_STALL      (1<<0)
#define USBD_EP0RDSTAT            0xB0200040
#define USBD_EP0WRSTAT            0xB0200044
#define USBD_EP2WRSTAT            0xB0200048
#define USBD_EP3WRSTAT            0xB020004C
#define USBD_EP4RDSTAT            0xB0200050
#define USBD_EP5RDSTAT            0xB0200054
  #define USBDEV_FSTAT_FLUSH     (1<<6)
  #define USBDEV_FSTAT_UF        (1<<5)
  #define USBDEV_FSTAT_OF        (1<<4)
  #define USBDEV_FSTAT_FCNT_BIT  0
  #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
#define USBD_ENABLE               0xB0200058
  #define USBDEV_ENABLE (1<<1)
  #define USBDEV_CE     (1<<0)

#endif /* !CONFIG_SOC_AU1200 */

/* Ethernet Controllers  */

/* 4 byte offsets from AU1000_ETH_BASE */
#define MAC_CONTROL                     0x0