au1000.h

skyeye for pxa270

#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
#endif

/***********************************************************************/

#ifdef CONFIG_SOC_AU1550
#define	MEM_PHYS_ADDR		0x14000000
#define	STATIC_MEM_PHYS_ADDR	0x14001000
#define	IC0_PHYS_ADDR		0x10400000
#define	IC1_PHYS_ADDR		0x11800000
#define	USBH_PHYS_ADDR		0x14020000
#define	USBD_PHYS_ADDR		0x10200000
#define PCI_PHYS_ADDR		0x14005000
#define	MAC0_PHYS_ADDR		0x10500000
#define	MAC1_PHYS_ADDR		0x10510000
#define	MACEN_PHYS_ADDR		0x10520000
#define	MACDMA0_PHYS_ADDR	0x14004000
#define	MACDMA1_PHYS_ADDR	0x14004200
#define	UART0_PHYS_ADDR		0x11100000
#define	UART1_PHYS_ADDR		0x11200000
#define	UART3_PHYS_ADDR		0x11400000
#define GPIO2_PHYS_ADDR		0x11700000
#define	SYS_PHYS_ADDR		0x11900000
#define	DDMA_PHYS_ADDR		0x14002000
#define PE_PHYS_ADDR		0x14008000
#define PSC0_PHYS_ADDR	 	0x11A00000
#define PSC1_PHYS_ADDR	 	0x11B00000
#define PSC2_PHYS_ADDR	 	0x10A00000
#define PSC3_PHYS_ADDR	 	0x10B00000
#define PCI_MEM_PHYS_ADDR     0x400000000ULL
#define PCI_IO_PHYS_ADDR      0x500000000ULL
#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
#endif

/***********************************************************************/

#ifdef CONFIG_SOC_AU1200
#define	MEM_PHYS_ADDR		0x14000000
#define	STATIC_MEM_PHYS_ADDR	0x14001000
#define AES_PHYS_ADDR		0x10300000
#define CIM_PHYS_ADDR		0x14004000
#define	IC0_PHYS_ADDR		0x10400000
#define	IC1_PHYS_ADDR		0x11800000
#define USBM_PHYS_ADDR		0x14020000
#define	USBH_PHYS_ADDR		0x14020100
#define	UART0_PHYS_ADDR		0x11100000
#define	UART1_PHYS_ADDR		0x11200000
#define GPIO2_PHYS_ADDR		0x11700000
#define	SYS_PHYS_ADDR		0x11900000
#define	DDMA_PHYS_ADDR		0x14002000
#define PSC0_PHYS_ADDR	 	0x11A00000
#define PSC1_PHYS_ADDR	 	0x11B00000
#define SD0_PHYS_ADDR		0x10600000
#define SD1_PHYS_ADDR		0x10680000
#define LCD_PHYS_ADDR		0x15000000
#define SWCNT_PHYS_ADDR		0x1110010C
#define MAEFE_PHYS_ADDR		0x14012000
#define MAEBE_PHYS_ADDR		0x14010000
#define PCMCIA_IO_PHYS_ADDR   0xF00000000ULL
#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
#define PCMCIA_MEM_PHYS_ADDR  0xF80000000ULL
#endif


/* Static Bus Controller */
#define MEM_STCFG0                 0xB4001000
#define MEM_STTIME0                0xB4001004
#define MEM_STADDR0                0xB4001008

#define MEM_STCFG1                 0xB4001010
#define MEM_STTIME1                0xB4001014
#define MEM_STADDR1                0xB4001018

#define MEM_STCFG2                 0xB4001020
#define MEM_STTIME2                0xB4001024
#define MEM_STADDR2                0xB4001028

#define MEM_STCFG3                 0xB4001030
#define MEM_STTIME3                0xB4001034
#define MEM_STADDR3                0xB4001038

#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
#define MEM_STNDCTL                0xB4001100
#define MEM_STSTAT                 0xB4001104

#define MEM_STNAND_CMD                  (0x0)
#define MEM_STNAND_ADDR                 (0x4)
#define MEM_STNAND_DATA                (0x20)
#endif

/* Interrupt Controller 0 */
#define IC0_CFG0RD                 0xB0400040
#define IC0_CFG0SET                0xB0400040
#define IC0_CFG0CLR                0xB0400044

#define IC0_CFG1RD                 0xB0400048
#define IC0_CFG1SET                0xB0400048
#define IC0_CFG1CLR                0xB040004C

#define IC0_CFG2RD                 0xB0400050
#define IC0_CFG2SET                0xB0400050
#define IC0_CFG2CLR                0xB0400054

#define IC0_REQ0INT                0xB0400054
#define IC0_SRCRD                  0xB0400058
#define IC0_SRCSET                 0xB0400058
#define IC0_SRCCLR                 0xB040005C
#define IC0_REQ1INT                0xB040005C

#define IC0_ASSIGNRD               0xB0400060
#define IC0_ASSIGNSET              0xB0400060
#define IC0_ASSIGNCLR              0xB0400064

#define IC0_WAKERD                 0xB0400068
#define IC0_WAKESET                0xB0400068
#define IC0_WAKECLR                0xB040006C

#define IC0_MASKRD                 0xB0400070
#define IC0_MASKSET                0xB0400070
#define IC0_MASKCLR                0xB0400074

#define IC0_RISINGRD               0xB0400078
#define IC0_RISINGCLR              0xB0400078
#define IC0_FALLINGRD              0xB040007C
#define IC0_FALLINGCLR             0xB040007C

#define IC0_TESTBIT                0xB0400080

/* Interrupt Controller 1 */
#define IC1_CFG0RD                 0xB1800040
#define IC1_CFG0SET                0xB1800040
#define IC1_CFG0CLR                0xB1800044

#define IC1_CFG1RD                 0xB1800048
#define IC1_CFG1SET                0xB1800048
#define IC1_CFG1CLR                0xB180004C

#define IC1_CFG2RD                 0xB1800050
#define IC1_CFG2SET                0xB1800050
#define IC1_CFG2CLR                0xB1800054

#define IC1_REQ0INT                0xB1800054
#define IC1_SRCRD                  0xB1800058
#define IC1_SRCSET                 0xB1800058
#define IC1_SRCCLR                 0xB180005C
#define IC1_REQ1INT                0xB180005C

#define IC1_ASSIGNRD               0xB1800060
#define IC1_ASSIGNSET              0xB1800060
#define IC1_ASSIGNCLR              0xB1800064

#define IC1_WAKERD                 0xB1800068
#define IC1_WAKESET                0xB1800068
#define IC1_WAKECLR                0xB180006C

#define IC1_MASKRD                 0xB1800070
#define IC1_MASKSET                0xB1800070
#define IC1_MASKCLR                0xB1800074

#define IC1_RISINGRD               0xB1800078
#define IC1_RISINGCLR              0xB1800078
#define IC1_FALLINGRD              0xB180007C
#define IC1_FALLINGCLR             0xB180007C

#define IC1_TESTBIT                0xB1800080

/* Interrupt Configuration Modes */
#define INTC_INT_DISABLED                0
#define INTC_INT_RISE_EDGE             0x1
#define INTC_INT_FALL_EDGE             0x2
#define INTC_INT_RISE_AND_FALL_EDGE    0x3
#define INTC_INT_HIGH_LEVEL            0x5
#define INTC_INT_LOW_LEVEL             0x6
#define INTC_INT_HIGH_AND_LOW_LEVEL    0x7

/* Interrupt Numbers */
/* Au1000 */
#ifdef CONFIG_SOC_AU1000
#define AU1000_UART0_INT          0
#define AU1000_UART1_INT          1 /* au1000 */
#define AU1000_UART2_INT          2 /* au1000 */
#define AU1000_UART3_INT          3
#define AU1000_SSI0_INT           4 /* au1000 */
#define AU1000_SSI1_INT           5 /* au1000 */
#define AU1000_DMA_INT_BASE       6
#define AU1000_TOY_INT            14
#define AU1000_TOY_MATCH0_INT     15
#define AU1000_TOY_MATCH1_INT     16
#define AU1000_TOY_MATCH2_INT     17
#define AU1000_RTC_INT            18
#define AU1000_RTC_MATCH0_INT     19
#define AU1000_RTC_MATCH1_INT     20
#define AU1000_RTC_MATCH2_INT     21
#define AU1000_IRDA_TX_INT        22 /* au1000 */
#define AU1000_IRDA_RX_INT        23 /* au1000 */
#define AU1000_USB_DEV_REQ_INT    24
#define AU1000_USB_DEV_SUS_INT    25
#define AU1000_USB_HOST_INT       26
#define AU1000_ACSYNC_INT         27
#define AU1000_MAC0_DMA_INT       28
#define AU1000_MAC1_DMA_INT       29
#define AU1000_I2S_UO_INT         30 /* au1000 */
#define AU1000_AC97C_INT          31
#define AU1000_GPIO_0             32
#define AU1000_GPIO_1             33
#define AU1000_GPIO_2             34
#define AU1000_GPIO_3             35
#define AU1000_GPIO_4             36
#define AU1000_GPIO_5             37
#define AU1000_GPIO_6             38
#define AU1000_GPIO_7             39
#define AU1000_GPIO_8             40
#define AU1000_GPIO_9             41
#define AU1000_GPIO_10            42
#define AU1000_GPIO_11            43
#define AU1000_GPIO_12            44
#define AU1000_GPIO_13            45
#define AU1000_GPIO_14            46
#define AU1000_GPIO_15            47
#define AU1000_GPIO_16            48
#define AU1000_GPIO_17            49
#define AU1000_GPIO_18            50
#define AU1000_GPIO_19            51
#define AU1000_GPIO_20            52
#define AU1000_GPIO_21            53
#define AU1000_GPIO_22            54
#define AU1000_GPIO_23            55
#define AU1000_GPIO_24            56
#define AU1000_GPIO_25            57
#define AU1000_GPIO_26            58
#define AU1000_GPIO_27            59
#define AU1000_GPIO_28            60
#define AU1000_GPIO_29            61
#define AU1000_GPIO_30            62
#define AU1000_GPIO_31            63

#define UART0_ADDR                0xB1100000
#define UART1_ADDR                0xB1200000
#define UART2_ADDR                0xB1300000
#define UART3_ADDR                0xB1400000

#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
#define USB_HOST_CONFIG           0xB017fffc

#define AU1000_ETH0_BASE      0xB0500000
#define AU1000_ETH1_BASE      0xB0510000
#define AU1000_MAC0_ENABLE       0xB0520000
#define AU1000_MAC1_ENABLE       0xB0520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1000 */

/* Au1500 */
#ifdef CONFIG_SOC_AU1500
#define AU1500_UART0_INT          0
#define AU1000_PCI_INTA           1 /* au1500 */
#define AU1000_PCI_INTB           2 /* au1500 */
#define AU1500_UART3_INT          3
#define AU1000_PCI_INTC           4 /* au1500 */
#define AU1000_PCI_INTD           5 /* au1500 */
#define AU1000_DMA_INT_BASE       6
#define AU1000_TOY_INT            14
#define AU1000_TOY_MATCH0_INT     15
#define AU1000_TOY_MATCH1_INT     16
#define AU1000_TOY_MATCH2_INT     17
#define AU1000_RTC_INT            18
#define AU1000_RTC_MATCH0_INT     19
#define AU1000_RTC_MATCH1_INT     20
#define AU1000_RTC_MATCH2_INT     21
#define AU1500_PCI_ERR_INT        22
#define AU1000_USB_DEV_REQ_INT    24
#define AU1000_USB_DEV_SUS_INT    25
#define AU1000_USB_HOST_INT       26
#define AU1000_ACSYNC_INT         27
#define AU1500_MAC0_DMA_INT       28
#define AU1500_MAC1_DMA_INT       29
#define AU1000_AC97C_INT          31
#define AU1000_GPIO_0             32
#define AU1000_GPIO_1             33
#define AU1000_GPIO_2             34
#define AU1000_GPIO_3             35
#define AU1000_GPIO_4             36
#define AU1000_GPIO_5             37
#define AU1000_GPIO_6             38
#define AU1000_GPIO_7             39
#define AU1000_GPIO_8             40
#define AU1000_GPIO_9             41
#define AU1000_GPIO_10            42
#define AU1000_GPIO_11            43
#define AU1000_GPIO_12            44
#define AU1000_GPIO_13            45
#define AU1000_GPIO_14            46
#define AU1000_GPIO_15            47
#define AU1500_GPIO_200           48
#define AU1500_GPIO_201           49
#define AU1500_GPIO_202           50
#define AU1500_GPIO_203           51
#define AU1500_GPIO_20            52
#define AU1500_GPIO_204           53
#define AU1500_GPIO_205           54
#define AU1500_GPIO_23            55
#define AU1500_GPIO_24            56
#define AU1500_GPIO_25            57
#define AU1500_GPIO_26            58
#define AU1500_GPIO_27            59
#define AU1500_GPIO_28            60
#define AU1500_GPIO_206           61
#define AU1500_GPIO_207           62
#define AU1500_GPIO_208_215       63

/* shortcuts */
#define INTA AU1000_PCI_INTA
#define INTB AU1000_PCI_INTB
#define INTC AU1000_PCI_INTC
#define INTD AU1000_PCI_INTD

#define UART0_ADDR                0xB1100000
#define UART3_ADDR                0xB1400000

#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
#define USB_HOST_CONFIG           0xB017fffc

#define AU1500_ETH0_BASE	  0xB1500000
#define AU1500_ETH1_BASE	  0xB1510000
#define AU1500_MAC0_ENABLE       0xB1520000
#define AU1500_MAC1_ENABLE       0xB1520004
#define NUM_ETH_INTERFACES 2
#endif /* CONFIG_SOC_AU1500 */

/* Au1100 */
#ifdef CONFIG_SOC_AU1100
#define AU1100_UART0_INT          0
#define AU1100_UART1_INT          1
#define AU1100_SD_INT             2
#define AU1100_UART3_INT          3
#define AU1000_SSI0_INT           4
#define AU1000_SSI1_INT           5
#define AU1000_DMA_INT_BASE       6
#define AU1000_TOY_INT            14
#define AU1000_TOY_MATCH0_INT     15
#define AU1000_TOY_MATCH1_INT     16
#define AU1000_TOY_MATCH2_INT     17
#define AU1000_RTC_INT            18
#define AU1000_RTC_MATCH0_INT     19
#define AU1000_RTC_MATCH1_INT     20
#define AU1000_RTC_MATCH2_INT     21
#define AU1000_IRDA_TX_INT        22
#define AU1000_IRDA_RX_INT        23
#define AU1000_USB_DEV_REQ_INT    24
#define AU1000_USB_DEV_SUS_INT    25
#define AU1000_USB_HOST_INT       26
#define AU1000_ACSYNC_INT         27
#define AU1100_MAC0_DMA_INT       28
#define	AU1100_GPIO_208_215	29