decoder.c

skyeye for pxa270

				case MADD:
				{
					UInt64 temp1 = mstate->hi << 32 + mstate->lo;
					UInt64 temp2 = mstate->gpr[rs(instr)] * mstate->gpr[rt(instr)] + temp1;
					mstate->hi = (temp2 >> 32) & (~0x0);
					mstate->lo = temp2 & (~0x0);
					return nothing_special;
				}	
                                case FMUL:
                                {
                                        mstate->gpr[rd(instr)] = mstate->gpr[rs(instr)] * mstate->gpr[rt(instr)];
                                        return nothing_special;
                                }
				case CVT_S://CLZ:
				{
					int i = 31;
					for(i; i >= 0;i--)
						if( mstate->gpr[rs(instr)] & (1 << i))
							break;
						else
							continue;
					 mstate->gpr[rd(instr)] = 31 - i;
                                        return nothing_special;
				}
				default:
		                        // Load Doubleword Right
                		        process_reserved_instruction(mstate);
		                        return nothing_special;
			}
                }

	
		case LB:
    		{
			// Load Byte
			UInt32 x; 
			UInt32 y = 0;

			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa;
			if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC)
				return nothing_special;
			/*
			if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC){
					return nothing_special;
			}*/
			load(mstate, va, pa, &y, 1);
			
			x = sign_extend_UInt32(y & (0xff), 8); //Shi yang 2006-08-10, Sign extend

			mstate->gpr[rt(instr)] = x;

			return nothing_special;
    		}
    		case LH:
    		{
			// Load Halfword
			if (mstate->sync_bit)
				sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];

			if (bit(va, 0)) //Check alignment
				process_address_error(data_load, va);
			PA pa;
			if(translate_vaddr(mstate,va, data_load, &pa) != TLB_SUCC)
				return nothing_special; //Shi yang 2006-08-10
			UInt32 x; 
			UInt32 y = 0;
			load(mstate, va, pa, &y, 2);
			x = sign_extend_UInt32(y & (0xffff), 16); //Shi yang 2006-08-10, Sign extend

			mstate->gpr[rt(instr)] = x;
			return nothing_special;
    		}
    		case LWL:
    		{
			// Load Word Left
			if (mstate->sync_bit)
				sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa;
			if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC)
				return nothing_special; //Shi yang 2006-08-10
			UInt32 mem;
			UInt32 y = 0;
			load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4);
			mem = y & (0xffffffff);

			UInt32 reg = mstate->gpr[rt(instr)];

			int syscmd = bits(va, 1, 0);
			if (!big_endian_cpu(mstate))
			    	syscmd ^= bitsmask(1, 0);

			reg = copy_bits(reg, mem, 31, syscmd * 8);
			mstate->gpr[rt(instr)] = reg;

			return nothing_special;
    		}
    		case LW:
    		{
			// Load Word
			if (mstate->sync_bit)
  			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			if (bits(va, 1, 0)) //Check alignment
				process_address_error(mstate,data_load, va);
			PA pa;
			if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC)
				return nothing_special; //Shi yang 2006-08-10
			UInt32 x;
			UInt32 y = 0;
			load(mstate, va, pa, &y, 4);

			mstate->gpr[rt(instr)] = y;
			return nothing_special;
    		}
		case LBU:
    		{
			// Load Byte Unsigned
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa;
			if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC)
				return nothing_special; //Shi yang 2006-08-10
			UInt32 y = 0;
			UInt32 x;
			load(mstate, va, pa, &y, 1);
			x = y & 0xffL; //Shi yang 2006-08-25
			mstate->gpr[rt(instr)] = x;

			return nothing_special;
    		}
		case LHU:
    		{
			// Load Halfword Unsigned
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			if (bit(va, 0)) //Check alignment
		    		process_address_error(mstate,data_load, va);
			PA pa;
			if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC)
				return nothing_special; //Shi yang 2006-08-10
			UInt16 x;
			UInt32 y = 0;
			load(mstate, va, pa, &y, 2);
			x = y & 0xffffL; //Shi yang 2006-08-25

			mstate->gpr[rt(instr)] = x;
			return nothing_special;
    		}
		case LWR:
    		{
			// Load Word Right
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa;
			if(translate_vaddr(mstate,va, data_load, &pa))
				return nothing_special; //Shi yang 2006-08-10
			UInt32 mem;
			UInt32 y = 0;
			load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4);
			mem = y & (0xffffffff);

			UInt32 reg = mstate->gpr[rt(instr)];
			int syscmd = bits(va, 1, 0);
			if (big_endian_cpu(mstate))
			    	syscmd ^= bitsmask(1, 0);
			reg = copy_bits(reg, bits(mem, 31, syscmd * 8), 31 - syscmd * 8, 0);
			mstate->gpr[rt(instr)] = reg;
			return nothing_special;
    		}
		case LWU:
		{
			// Load Word Unsigned
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SB:
    		{
			// Store Byte
			if (mstate->sync_bit)
	    			sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa;
			if(translate_vaddr(mstate,va, data_store, &pa))
				return nothing_special; //Shi yang 2006-08-10
			store(mstate, mstate->gpr[rt(instr)], va, pa, 1); // Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
	    	case SH:
    		{
			// Store Halfword
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			if (bit(va, 0)) //Check alignment
			    	process_address_error(mstate,data_store, va);
			PA pa;
			if(translate_vaddr(mstate, va, data_store, &pa))
				return nothing_special; //Shi yang 2006-08-10
			store(mstate, mstate->gpr[rt(instr)], va, pa, 2); //Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
		case SWL:
    		{
			// Store Word Left
			if (mstate->sync_bit)
				sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa;
			if(translate_vaddr(mstate, va, data_store, &pa))
				return nothing_special; //Shi yang 2006-08-10
			UInt32 mem;
			UInt32 y = 0;
			load(mstate, round_down(va, 4), round_down(pa, 4), &y, 4);
			mem = y & (0xffffffff);
	
			UInt32 reg = mstate->gpr[rt(instr)];
			int syscmd = bits(va, 1, 0);
			if (!big_endian_cpu(mstate))
			    	syscmd ^= bitsmask(1, 0);
			mem = copy_bits(mem, bits(reg, 31, syscmd * 8), 31 - syscmd * 8, 0);
			store(mstate, mem, round_down(va, 4), round_down(pa, 4), 4); //Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
    		case SW:
    		{
			// Store Word
			if (mstate->sync_bit)
		    		sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			if (bits(va, 1, 0)) //Check alignment
			{
				fprintf(stderr," in %s,address unaligned va=0x%x,pc=0x%x\n", __FUNCTION__, va, mstate->pc);
				skyeye_exit(-1);
			    	process_address_error(mstate,data_store, va);
			}
			PA pa;
			if(translate_vaddr(mstate,va, data_store, &pa) != TLB_SUCC)
				return nothing_special; //Shi yang 2006-08-10
			store(mstate, mstate->gpr[rt(instr)], va, pa, 4); //Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
    		case SDL:
    		{
			// Store Doubleword Left
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SDR:
    		{
			// Store Doubleword Right
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SWR:
    		{
			// Store Word Right
			if (mstate->sync_bit)
			    	sync();
			VA va = sign_extend_UInt32(offset(instr), 16) + mstate->gpr[base(instr)];
			PA pa;
			if(translate_vaddr(mstate, va, data_store, &pa) != TLB_SUCC)
				return nothing_special; //Shi yang 2006-08-10
			UInt32 mem;
			UInt32 y = 0;
			load(mstate,round_down(va, 4), round_down(pa, 4),&y,4);
			mem = y & (0xffffffff);
	
			UInt32 reg = mstate->gpr[rt(instr)];
			int syscmd = bits(va, 1, 0);
			if (big_endian_cpu(mstate))
			    	syscmd ^= bitsmask(1, 0);
			mem = copy_bits(mem, reg, 31, syscmd * 8);
			store(mstate, mem, round_down(va, 4), round_down(pa, 4), 4); //Fix me: Shi yang 2006-08-10
			return nothing_special;
    		}
    		case CACHE: //Nedved's cache instruction. Shi yang 2006-08-24
    		{
			// Cache
			return nothing_special;
    		}
		case LL:
    		{
			// Load Linked
			//int va = mstate->gpr[base(instr)] + offset(instr);
			int va = mstate->gpr[base(instr)] + sign_extend_UInt32(offset(instr), 16);
			PA pa;
			if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC)
				return nothing_special;
			int data;
			mips_mem_read(pa, &data, 4);	
			mstate->gpr[rt(instr)] = data;
			//process_reserved_instruction(mstate);
			return nothing_special;
    		}
		case LWC1:
    		{
			// Load Word to Coprocessor 1
			return nothing_special; //Shi yang 2006-08-31
    		}
	    	case LWC2:
    		{
			// Load Word to Coprocessor 2
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
		case LLD:
    		{
			// Load Linked Doubleword
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case LDC1:
    		{
			// Load Doubleword To Coprocessor 1
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
	    	case LDC2:
    		{
			// Load Doubleword To Coprocessor 2
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case LD:
    		{
			// Load Doubleword
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SC:
    		{
			// Store Conditional
                        //int va = mstate->gpr[base(instr)] + offset(instr);
			int va = mstate->gpr[base(instr)] + sign_extend_UInt32(offset(instr), 16);
                        PA pa;
			if(translate_vaddr(mstate, va, data_load, &pa) != TLB_SUCC)
				return nothing_special;
                        int data;
			data = mstate->gpr[rt(instr)];
			
			/*
			if(mstate->pc == 0x8012a858){
				fprintf(stderr, "In SC,data=0x%x,va=0x%x\n", data, va);
				if(va == 0x81179a00){
					fprintf(stderr, "Write to %d\n",va);
					skyeye_exit(-1);
				}
			}
			*/
                        mips_mem_write(pa, &data, 4);
                        mstate->gpr[rt(instr)] = 1;

			//process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SWC1:
    		{
			// Store Word From Coprocessor 1
			return nothing_special; //Shi yang 2006-08-31
    		}
		case SWC2:
    		{
			// Store Word From Coprocessor 2
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SCD:
    		{
			// Store Conditional
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SDC1:
    		{
			// Store Doubleword From Coprocessor 1
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
	    	case SDC2:
    		{
			// Store Doubleword From Coprocessor 2
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case SD:
    		{
			// Store Doubleword
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		default:
			// Reserved instruction.
			process_reserved_instruction(mstate);
			return nothing_special;
    	}
}