decoder.c

skyeye for pxa270

				case TNE:
				{
				    	// Trap If Not Equal
					if( mstate->gpr[rs(instr)] != mstate->gpr[rt(instr)])
						fprintf(stderr,"trap happened in %s at 0x%x.\n", __FUNCTION__, mstate->pc);
					//process_reserved_instruction(mstate);
					//skyeye_exit(-1);
					
					return nothing_special;
				}
				case DSLL:
				{
				    	// Doubleword Shift Left Logical
					process_reserved_instruction(mstate);
					return nothing_special;
				}
				case DSRL:
				{
				    	// Doubleword Shift Right Logical
					process_reserved_instruction(mstate);
					return nothing_special;
				}
				case DSRA:
				{
			    		// Doubleword Shift Right Arithmetic
					process_reserved_instruction(mstate);
					return nothing_special;
				}
				case DSLL32:
				{
			    		// Doubleword Shift Left Logical + 32
					process_reserved_instruction(mstate);
					return nothing_special;
				}
				case DSRL32:
				{
				    	// Doubleword Shift Right Logical + 32 
					process_reserved_instruction(mstate);
					return nothing_special;
				}
				case DSRA32:
				{
			    		// Doubleword Shift Right Arithmetic + 32
					process_reserved_instruction(mstate);
					return nothing_special;
				}
				default:
			    		// Reserved instruction
					process_reserved_instruction(mstate);
				    	return nothing_special;
			}// switch (function(instr)) {
		}//case SPECIAL:
    	
		case REGIMM:
    		{
			switch (rt(instr)) {
				case BLTZ:
				{
	   			 	// Branch On Less Than Zero
				    	Int32 x = mstate->gpr[rs(instr)];
	    				if (x < 0) {
						VA off = sign_extend_UInt32(offset(instr), 16);
						mstate->branch_target = mstate->pc + 4 + (off << 2);
	    				} else {
						mstate->branch_target = mstate->pc + 8;
	    				}
			    		if (mstate->pipeline == branch_delay) {
						printf("Can't handle branch in branch delay slot\n");
					}
				    	return branch_delay;
				}
				case BGEZ:
				{
				    	// Branch On greater Than Zero
				    	Int32 x = mstate->gpr[rs(instr)];
				    	if (x >= 0) {
						VA off = sign_extend_UInt32(offset(instr), 16);
						mstate->branch_target = mstate->pc + 4 + (off << 2);
	    				} else {
						mstate->branch_target = mstate->pc + 8;
	    				}
			    		if (mstate->pipeline == branch_delay) {
						printf("Can't handle branch in branch delay slot\n");
					}
				    	return branch_delay;
				}
				case BLTZL:
				{
			    		// Branch On Less Than Zero Likely
					return nothing_special;
				}
				case BGEZL:
				{
				    	// Branch On Greater Than Or Equal To Zero Likely
					return nothing_special;
				}
				case TGEI:
				{
				    	// Trap If Greater Than Or Equal Immediate
					return nothing_special;
				}
				case TGEIU:
				{
			    		// Trap If Greater Than Or Equal Immediate Unsigned
				    	return nothing_special;
				}
				case TLTI:
				{
			    		// Trap If Less Than Immediate
				    	return nothing_special;
				}
				case TLTIU:
				{
			    		// Trap If Less Than Immediate Unsigned
				    	return nothing_special;
				}
				case TEQI:
				{
			    		// Trap If Equal Immediate
				    	return nothing_special;
				}
				case TNEI:
				{
			    		// Trap If Not Equal Immediate
				    	return nothing_special;
				}
				case BLTZAL:
				{
				    	// Branch On Less Than Zero And Link
				    	Int32 x = mstate->gpr[rs(instr)];
				    	mstate->gpr[31] = mstate->pc + 8;
				    	if (x < 0) {
						VA off = sign_extend_UInt32(offset(instr), 16);
						mstate->branch_target = mstate->pc + 4 + (off << 2);
	    				} else {
				    		mstate->branch_target = mstate->pc + 8;
	    				}
	    				if (mstate->pipeline == branch_delay) {
						printf("Can't handle branch in branch delay slot\n");
					}
				    	return branch_delay;
				}
				case BGEZAL:
				{
				    	// Branch On Greater Than Or Equal To Zero And Link
				    	Int32 x = mstate->gpr[rs(instr)];
				    	mstate->gpr[31] = mstate->pc + 8;
				    	if (x >= 0) {
						VA off = sign_extend_UInt32(offset(instr), 16);
						mstate->branch_target = mstate->pc + 4 + (off << 2);
					} else {
						mstate->branch_target = mstate->pc + 8;
	    				}		
				    	if (mstate->pipeline == branch_delay) {
						printf("Can't handle branch in branch delay slot\n");
					}
				    	return branch_delay;
				}
				case BLTZALL:
				{
			    		// Branch On Less Than Zero And Link Likely
					return nothing_special;
				}
				case BGEZALL:
				{
			    		// Branch On Greater Than Or Equal To Zero And Link Likely
					return nothing_special;
				}
				default:
				    	process_reserved_instruction(mstate);
				    	return nothing_special; //Fix me. Shi yang 2006-08-09
			}
    		}//case REGIMM:
    		case J:
    		{
			// Jump
			VA msb = clear_bits(mstate->pc + 4, 27, 0);
			mstate->branch_target = msb | (target(instr) << 2);
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}
			return branch_delay;
    		}
		case JAL:
    		{
			// Jump And Link
			mstate->gpr[31] = mstate->pc + 8;
			VA msb = clear_bits(mstate->pc + 4, 27, 0);
			mstate->branch_target = msb | (target(instr) << 2);
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}
			return branch_delay;
    		}
    		case BEQ:
    		{
			// Branch On Equal
			if (mstate->gpr[rs(instr)] == mstate->gpr[rt(instr)]) {
				VA off = sign_extend_UInt32(offset(instr), 16);
			    	mstate->branch_target = mstate->pc + 4 + (off << 2);
			} else {
			    	mstate->branch_target = mstate->pc + 8;
			}
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}

			return branch_delay;
    		}
    		case BNE:
    		{
			// Branch On Not Equal
			if (mstate->gpr[rs(instr)] != mstate->gpr[rt(instr)]) {
				VA off = sign_extend_UInt32(offset(instr), 16);
	   			 mstate->branch_target = mstate->pc + 4 + (off << 2);
			} else {
			    	mstate->branch_target = mstate->pc + 8;
			}
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}
	
			return branch_delay;
    		}
    		case BLEZ:
    		{
			// Branch On Less Than Or Equal To Zero
			Int32 x = mstate->gpr[rs(instr)];
			if (x <= 0) {
			    	VA off = sign_extend_UInt32(offset(instr), 16);
			    	mstate->branch_target = mstate->pc + 4 + (off << 2);
			} else {
				mstate->branch_target = mstate->pc + 8;
			}
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}

			return branch_delay;
    		}
		case BGTZ:
    		{
			// Branch On Greater Than Zero
			Int32 x = mstate->gpr[rs(instr)];
			if (x > 0) {
			    	VA off = sign_extend_UInt32(offset(instr), 16);
			    	mstate->branch_target = mstate->pc + 4 + (off << 2);
			} else {
			    	mstate->branch_target = mstate->pc + 8;
			}
			if (mstate->pipeline == branch_delay) {
				printf("Can't handle branch in branch delay slot");
			}

			return branch_delay;
    		}
    		case ADDI:
    		{
			// Add Immediate
			UInt32 x = mstate->gpr[rs(instr)];
			UInt32 y = sign_extend_UInt32(immediate(instr), 16);
			UInt32 z = x + y;
			// Overflow occurs is sign(x) == sign(y) != sign(z).
			if (bit(x ^ y, 31) == 0 && bit(x ^ z, 31) != 0)
			    	process_integer_overflow(mstate);
			mstate->gpr[rt(instr)] = z;
			return nothing_special;
    		}
		case ADDIU:
    		{
			/* confused, signed or unsigned ?? */
			// Add Immediate Unsigned
			UInt32 x = mstate->gpr[rs(instr)];
			Int32 y = sign_extend_UInt32(immediate(instr), 16);
			UInt32 z = x + y;
			//fprintf(skyeye_logfd, "0x%d,0x%d,0x%d, in 0x%x\n", x ,y, z, mstate->pc);
			mstate->gpr[rt(instr)] = z;
		
			return nothing_special;
    		}
		case SLTI:
    		{
			// Set On Less Than Immediate
			Int32 x = mstate->gpr[rs(instr)];
			Int32 y = sign_extend_UInt32(immediate(instr), 16);
			mstate->gpr[rt(instr)] = (x < y);
	
			return nothing_special;
    		}
	    	case SLTIU:
    		{
			// Set On Less Than Immediate Unsigned
			UInt32 x = mstate->gpr[rs(instr)];
			UInt32 y = sign_extend_UInt32(immediate(instr), 16);
			mstate->gpr[rt(instr)] = (x < y);

			return nothing_special;
    		}
	    	case ANDI:
    		{
			// And Immediate
			UInt16 x = mstate->gpr[rs(instr)];
			UInt16 imm = zero_extend(immediate(instr), 16);
			mstate->gpr[rt(instr)] = x & imm; //Shi yang 2006-08-31
			return nothing_special;
    		}
	    	case ORI:
    		{
			// Or Immediate
			UInt32 x = mstate->gpr[rs(instr)]; //Shi yang 2006-08-09
			UInt16 imm = immediate(instr);
			mstate->gpr[rt(instr)] = x | imm;

			return nothing_special;
    		}
	    	case XORI:
    		{
			// Exclusive Or Immediate
			UInt32 x = mstate->gpr[rs(instr)];
			UInt32 imm = immediate(instr);
			mstate->gpr[rt(instr)] = x ^ imm;

			return nothing_special;
    		}
    		case LUI:
    		{
			// Load Upper Immediate
			UInt32 imm = immediate(instr);
			imm <<= 16;
			mstate->gpr[rt(instr)] = imm;

			return nothing_special;
    		}
	    	case COP0:
    		{
			// Coprocessor 0 Operation
			return decode_cop0(mstate, instr);
    		}
	    	case COP1:
    		{
			return decode_cop1(mstate, instr);
			// Coprocessor 1 Operation
			//process_reserved_instruction(mstate);
    		}
		case COP2:
    		{
			// Coprocessor 2 Operation
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
		case PREF:
		{
			//fprintf(stderr, "PREF instruction,pc=0x%x\n",mstate->pc);
			return nothing_special;
		}
	    	case BEQL:
    		{
			// Branch On Equal Likely
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case BNEL:
    		{
			// Branch On Not Equal Likely
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case BLEZL:
    		{
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case BGTZL:
    		{
			// Branch On Greater Than Zero Likely
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case DADDI:
    		{
			// Doubleword Add Immediate
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
	    	case DADDIU:
    		{
			// Doubleword Add Immediate Unsigned
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case LDL:
    		{
			// Load Doubleword Left
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
    		case LDR:
    		{
			// Load Doubleword Right
			process_reserved_instruction(mstate);
			return nothing_special;
    		}
		case SPECIAL2:
		{
			
                        switch (function(instr)) {