mips_arch_interface.c

skyeye for pxa270

	 * improve the simulator's performance: something I cannot say about
	 * caches and JTLB.
   	 */

	PA pa; //Shi yang 2006-08-18
	VA va;
	Instr instr;
	int next_state;
	va = mstate->pc;
	if(translate_vaddr(mstate, va, instr_fetch, &pa) == TLB_SUCC){
		mips_mem_read(pa, &instr, 4);
		next_state = decode(mstate, instr);	
		//skyeye_exit(-1);
	}
	else{
		//fprintf(stderr, "Exception when get instruction!\n");
	}

	/* NOTE: mstate->pipeline is also possibely set in decode function */

	static int flag = 0;
	if(mstate->pc == 0x4001a0)
		flag = 0;
	if(flag)
		//fprintf(skyeye_logfd, "KSDBG:instr=0x%x,pa=0x%x, va=0x%x, sp=0x%x, ra=0x%x,s1=0x%x, v0=0x%x\n", instr, pa, va, mstate->gpr[29], mstate->gpr[31],mstate->gpr[17], mstate->gpr[2]);
		fprintf(skyeye_logfd, "KSDBG:instr=0x%x,pa=0x%x, va=0x%x, a0=0x%x, a1=0x%x, t0=0x%x, t1=0x%x, v0=0x%x, s8=0x%x\n", instr, pa, va, mstate->gpr[4], mstate->gpr[5], mstate->gpr[8], mstate->gpr[9], mstate->gpr[2], mstate->gpr[30]);
		//fprintf(skyeye_logfd, "KSDBG:instr=0x%x,pa=0x%x, va=0x%x,v0=0x%x,t0=0x%x\n", instr, pa, va, mstate->gpr[2], mstate->gpr[8]);
	/*if(mips_mem.rom[0][(0x1179a00 >> 2)] != 0){
		if(mips_mem.rom[0][(0x1179a00 >> 2)] != 0x81179b28)
			fprintf(stderr, "Value changed:0x81179a00 = 0x%x,pc=0x%x\n", mips_mem.rom[0][(0x1179a00 >> 2)],mstate->pc);
	}*/

	switch (mstate->pipeline) {
		case nothing_special:
	    		mstate->pc += 4;
	    		break;
		case branch_delay:
		    	mstate->pc = mstate->branch_target;
		    	break;
		case instr_addr_error:
		    	process_address_error(mstate, instr_fetch, mstate->branch_target);
		case branch_nodelay: /* For syscall and TLB exp, we donot like to add pc */
			mstate->pipeline = nothing_special;
			return; /* do nothing */
	}
	mstate->pipeline = next_state;
	/* if interrupt is enabled? */
	if((mstate->cp0[SR] & (1 << SR_IEC)) && (mstate-> cp0[SR] & 1 << SR_IM7)){
		if(!(mstate->cp0[Cause] & 1 << Cause_IP7) && (!(mstate->cp0[SR] & 0x2)))
		{
			/* update counter value in cp0 */
			mstate->cp0[Count]++;
			//fprintf(stderr, "counter=0x%x,pc=0x%x\n", mstate->cp0[Count], mstate->pc);
			/* if timer int is not mask and counter value is equal to compare value */
			if(mstate->cp0[Count] >= mstate->cp0[Compare]){
			/* Set counter interrupt bit in IP section of Cause register */
				mstate->cp0[Cause] |= 1 << Cause_IP7;
			/* Set ExcCode to zero in Cause register */
				process_exception(mstate, EXC_Int, common_vector);
			}
		}
	}
	skyeye_config.mach->mach_io_do_cycle (mstate);	
}

static void 
mips_set_pc(UInt32 addr)
{
	mstate->pc = addr;
}

static UInt32 
mips_get_pc()
{
	return  mstate->pc;
}

static void
mips_write_byte (WORD addr, uint8_t v)
{
	mips_mem_write_byte (addr, v);
}

static void 
mips_write_byte64(UInt64 addr, UInt8 data)
{

}

static unsigned char 
mips_read_byte64(UInt64 addr)
{

}


extern void nedved_mach_init(void * state, machine_config_t * mach);
extern void au1100_mach_init(void * state, machine_config_t * mach);
extern void fulong_mach_init(void * state, machine_config_t * mach);

static machine_config_t mips_machines[] = {
	{"nedved", nedved_mach_init, NULL, NULL, NULL},
	{"au1100", au1100_mach_init, NULL, NULL, NULL},
};



static int 
mips_parse_cpu(const char* param[])
{
	return 1;
}

static int 
mips_parse_mach(machine_config_t * mach, const char* params[])
{
	int i;
	for (i = 0; i < (sizeof (mips_machines) / sizeof (machine_config_t));
	     i++) {
		if (!strncmp
		    (params[0], mips_machines[i].machine_name,
		     MAX_PARAM_NAME)) {
			skyeye_config.mach = &mips_machines[i];
			SKYEYE_INFO
				("mach info: name %s, mach_init addr %p\n",
				 skyeye_config.mach->machine_name,
				 skyeye_config.mach->mach_init);
			return 0;
		}
	}
	SKYEYE_ERR ("Error: Unkonw mach name \"%s\"\n", params[0]);
	return -1;

}

static int 
mips_parse_mem(int num_params, const char* params[])
{
	char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME];
	int i, num;
	mips_mem_config_t *mc = &mips_mem_config;
	mips_mem_bank_t *mb = mc->mem_banks;

	mc->bank_num = mc->current_num++;

	num = mc->current_num - 1;	/*mem_banks should begin from 0. */
	mb[num].filename[0] = '\0';
	for (i = 0; i < num_params; i++) {
		if (split_param (params[i], name, value) < 0)
			SKYEYE_ERR
				("Error: mem_bank %d has wrong parameter \"%s\".\n",
				 num, name);

		if (!strncmp ("map", name, strlen (name))) {
			if (!strncmp ("M", value, strlen (value))) {
				mb[num].read_byte = mips_real_read_byte;
				mb[num].write_byte = mips_real_write_byte;
				mb[num].read_halfword = mips_real_read_halfword;
				mb[num].write_halfword = mips_real_write_halfword;
				mb[num].read_word = mips_real_read_word;
				mb[num].write_word = mips_real_write_word;
				mb[num].read_doubleword = mips_real_read_doubleword;
				mb[num].write_doubleword = mips_real_write_doubleword;
				mb[num].type = MEMTYPE_RAM;
			}
			else if (!strncmp ("I", value, strlen (value))) {
				mb[num].read_byte = mips_io_read_byte;
				mb[num].write_byte = mips_io_write_byte;
				mb[num].read_halfword = mips_io_read_halfword;
				mb[num].write_halfword = mips_io_write_halfword;
				mb[num].read_word = mips_io_read_word;
				mb[num].write_word = mips_io_write_word;
				mb[num].read_doubleword = mips_io_read_doubleword;
				mb[num].write_doubleword = mips_io_write_doubleword;

				mb[num].type = MEMTYPE_IO;

				/*ywc 2005-03-30 */
			}
			else if (!strncmp ("F", value, strlen (value))) {
				mb[num].read_byte = mips_flash_read_byte;
				mb[num].write_byte = mips_flash_write_byte;
				mb[num].read_halfword = mips_flash_read_halfword;
				mb[num].write_halfword = mips_flash_write_halfword;
				mb[num].read_word = mips_flash_read_word;
				mb[num].write_word = mips_flash_write_word;
				mb[num].read_doubleword = mips_flash_read_doubleword;
				mb[num].write_doubleword = mips_flash_write_doubleword;
				mb[num].type = MEMTYPE_FLASH;

			}
			else {
				SKYEYE_ERR
					("Error: mem_bank %d \"%s\" parameter has wrong value \"%s\"\n",
					 num, name, value);
			}
		}
		else if (!strncmp ("type", name, strlen (name))) {
			//chy 2003-09-21: process type
			if (!strncmp ("R", value, strlen (value))) {
				if (mb[num].type == MEMTYPE_RAM)
					mb[num].type = MEMTYPE_ROM;
				mb[num].write_byte = mips_warn_write_byte;
				mb[num].write_halfword = mips_warn_write_halfword;
				mb[num].write_word = mips_warn_write_word;
			}
		}
		else if (!strncmp ("addr", name, strlen (name))) {

			if (value[0] == '0' && value[1] == 'x')
				mb[num].addr = strtoul (value, NULL, 16);
			else
				mb[num].addr = strtoul (value, NULL, 10);

		}
		else if (!strncmp ("size", name, strlen (name))) {

			if (value[0] == '0' && value[1] == 'x')
				mb[num].len = strtoul (value, NULL, 16);
			else
				mb[num].len = strtoul (value, NULL, 10);

		}
		else if (!strncmp ("file", name, strlen (name))) {
			strncpy (mb[num].filename, value, strlen (value) + 1);
		}
		else if (!strncmp ("boot", name, strlen (name))) {
			/*this must be the last parameter. */
			if (!strncmp ("yes", value, strlen (value)))
				skyeye_config.start_address = mb[num].addr;
		}
		else {
			SKYEYE_ERR
				("Error: mem_bank %d has unknow parameter \"%s\".\n",
				 num, name);
		}
	}

	return 0;
}

static int mips_ICE_read_byte(WORD addr, uint8_t *data){
	mips_mem_read(addr, (UInt32 *)data, 1);
	return 0;
}
static int mips_ICE_write_byte(WORD addr, uint8_t data){
#if 1
	extern mips_mem_bank_t *mips_global_mbp;
        /* if pa is located at kseg0 */
        if(addr >= 0x80000000 && addr < 0xA0000000)
                addr = addr & ~0x80000000;
        /* if pa is located at kseg1 */
        if(addr >= 0xA0000000 && addr < 0xC0000000)
                addr = addr & ~0xE0000000;


	uint8_t  *temp;
	 //get the memory bank of the address
        mips_global_mbp = mips_bank_ptr (addr);

        if (mips_global_mbp ) {
		temp = &(mips_mem.rom[mips_global_mbp -
                               mips_mem_config.mem_banks][(addr -
                            mips_global_mbp->addr) >> 2]);
		temp += addr & 0x3;
        	*temp = data ;
        } else {
                fprintf(stderr,"mips memory write error in %s, addr=0x%x,pc=0x%x..\n",__FUNCTION__,addr, mstate->pc);
                skyeye_exit(-1);
        }
#endif
    //  	mips_mem_write(addr, &data, 1);  
	return 0;
}

void 
init_mips_arch ()
{
	static arch_config_t mips_arch;
	mips_arch.arch_name = arch_name;
	mips_arch.init = mips_init_state;
	mips_arch.reset = mips_reset_state;
	mips_arch.step_once = mips_step_once;
	mips_arch.set_pc = mips_set_pc;
	mips_arch.get_pc = mips_get_pc;
	mips_arch.ICE_read_byte = mips_ICE_read_byte;
	mips_arch.ICE_write_byte = mips_ICE_write_byte;
	mips_arch.parse_cpu = mips_parse_cpu;
	mips_arch.parse_mach = mips_parse_mach;
	mips_arch.parse_mem = mips_parse_mem;
	register_arch (&mips_arch);
}