mips_arch_interface.c

skyeye for pxa270

/* Simulator for MIPS R3000 architecture.

		THIS SOFTWARE IS NOT COPYRIGHTED

   Cygnus offers the following for use in the public domain.  Cygnus
   makes no warranty with regard to the software or it's performance
   and the user accepts the software "AS IS" with all faults.

   CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
   THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

*/

#include "skyeye_config.h"
#include "emul.h"
#include <stdlib.h>
#include "mipsdef.h"
#include <stdio.h>

MIPS_State* mstate;
static char *arch_name = "mips";
mips_mem_config_t mips_mem_config;
extern mips_mem_state_t mips_mem;
extern FILE *skyeye_logfd;
extern int trace_level;
extern UInt8* mem_bunks;
extern void mips_mem_reset ();
extern UInt32 mips_real_read_byte (UInt32 addr);
extern UInt32 mips_real_read_halfword (UInt32 addr);
extern UInt32 mips_real_read_word (UInt32 addr);
extern UInt64 mips_real_read_doubleword (UInt32 addr);
extern void mips_real_write_byte (UInt32 addr, UInt32 data);
extern void mips_real_write_halfword ( UInt32 addr, UInt32 data);
extern void mips_real_write_word ( UInt32 addr, UInt32 data);
extern void mips_real_write_doubleword ( UInt32 addr, UInt64 data);

//IO address space
extern UInt32 mips_io_read_byte (UInt32 addr);
extern UInt32 mips_io_read_halfword (UInt32 addr);
extern UInt32 mips_io_read_word (UInt32 addr);
extern UInt64 mips_io_read_doubleword (UInt32 addr);
extern void mips_io_write_byte (UInt32 addr, UInt32 data);
extern void mips_io_write_halfword (UInt32 addr, UInt32 data);
extern void mips_io_write_word (UInt32 addr, UInt32 data);
extern void mips_io_write_doubleword (UInt32 addr, UInt64 data);

//Flash address space
extern UInt32 mips_flash_read_byte (UInt32 addr);
extern UInt32 mips_flash_read_halfword (UInt32 addr);
extern UInt32 mips_flash_read_word (UInt32 addr);
extern UInt64 mips_flash_read_doubleword ( UInt32 addr);
extern void mips_flash_write_byte (UInt32 addr, UInt32 data);
extern void mips_flash_write_halfword (UInt32 addr, UInt32 data);
extern void mips_flash_write_word (UInt32 addr, UInt32 data);
extern void mips_flash_write_doubleword (UInt32 addr, UInt64 data);

extern void mips_warn_write_byte (UInt32 addr, UInt32 data);
extern void mips_warn_write_halfword (UInt32 addr, UInt32 data);
extern void mips_warn_write_word (UInt32 addr, UInt32 data);
extern mips_mem_bank_t* mips_bank_ptr (UInt32 addr);
extern void mips_mem_write_byte (UInt32 phys_addr, UInt32 v);
extern void mips_mem_write_halfword (UInt32 phys_addr, UInt32 v);
extern void mips_mem_write_word (UInt32 phys_addr, UInt32 v);
extern void mips_mem_write_doubleword (UInt64 phys_addr, UInt64 v);
extern UInt32 mips_mem_read_byte (UInt32 phys_addr);
extern UInt32 mips_mem_read_halfword (UInt32 phys_addr);
extern UInt32 mips_mem_read_word (UInt32 phys_addr);
extern UInt64 mips_mem_read_doubleword (UInt64 phys_addr);
extern void mipsMul_WriteByte (MIPS_State* mstate, UInt32 vir_addr, UInt32 v);
extern void mips_mmu_write_byte (MIPS_State* mstate, UInt32 vir_addr, UInt32 v);


//chy 20060717
int SKYPRINTF(char * fmt,...)
{ 
	return 0;
}

void 
mips_init_set(UInt32 addr, UInt8 value, int size)
{

}

void 
mips_mem_read(UInt32 pa, UInt32 *data, int len)
{
	/* if pa is located at kseg0 */
	if(pa >= 0x80000000 && pa < 0xA0000000)
		pa = pa & ~0x80000000;
	/* if pa is located at kseg1 */
	if(pa >= 0xA0000000 && pa < 0xC0000000)
		pa = pa & ~0xE0000000;
	//if(pa >= 0x14a1a0 && pa <= 0x14c000)
	//	printf("###############read addr pa=0x%x,pc=0x%x\n", pa, mstate->pc);

	switch(len) {
		
        	case 1: {
			*data = mips_mem_read_byte(pa);
			break;
		}
	 	case 2: {
	 		*data = mips_mem_read_halfword(pa);
			break;
	 	}
	 	case 4: {
			*data = mips_mem_read_word(pa);
			break;
	 	}
		default:
			break;
	}

}

void 
mips_mem_write(UInt32 pa, const UInt32* data, int len)
{
	/* if pa is located at kseg0 */
        if(pa >= 0x80000000 && pa < 0xA0000000)
                pa = pa & ~0x80000000;
        /* if pa is located at kseg1 */
        if(pa >= 0xA0000000 && pa < 0xC0000000)
                pa = pa & ~0xE0000000;

	UInt32 addr = bits(pa, 31, 0);
	if(pa >= 0x14a1a0 && pa <= 0x14c000)
		printf("###############write addr pa=0x%x,pc=0x%x\n", addr, mstate->pc);
	switch(len) {
		
        	case 1: {
			mips_mem_write_byte(pa, *data);
			break;
		}
	 	case 2: {
	 		mips_mem_write_halfword(pa, *data);
			break;
	 	}
	 	case 4: {
			mips_mem_write_word(pa, *data);
			break;
	 	}
		default:
			fprintf(stderr, "unimplemented write for size %d in %s\n", len, __FUNCTION__);
			break;
	}
	return;
	
}

static void 
init_icache()
{
	int i;
	for(i = 0; i < Icache_log2_sets; i++)
	{  
		Icache_lru_init(mstate->icache.set[i].Icache_lru);
	}

}

static void 
init_dcache()
{
	int i;
	for(i = 0; i < Dcache_log2_sets; i++)
	{  
	      Dcache_lru_init(mstate->dcache.set[i].Dcache_lru);
	}
}

static void 
init_tlb()
{
	int i; 
	for(i = 0;i < tlb_map_size + 1; i++)
	{
		mstate->tlb_map[i] = NULL;
	}
}


static void 
mips_init_state()
{
	set_bit(mstate->mode, 2);
	mstate = (MIPS_State* )malloc(sizeof(MIPS_State));
	if (!mstate) {
		fprintf (stderr, "malloc error!\n");
		skyeye_exit (-1);
	}

	mstate->warm = 0;
	mstate->conf.ec = 4; //I don't know what should it be.

	// set the little endian as the default
	mstate->bigendSig = 0; //Shi yang 2006-08-18
	
	//No interrupt
	mstate->irq_pending = 0;

	mstate->cp0[SR] = 0x40004;
	
	init_icache();
	init_dcache();
	init_tlb();

	 /* mach init */
	if(skyeye_config.mach->mach_init)
        	skyeye_config.mach->mach_init (mstate, skyeye_config.mach);
	else{
		fprintf(stderr, "skyeye arch is not initializd correctly.\n");
		skyeye_exit(-1);
	}
		
}

static void 
mips_reset_state()
{
	mips_mem_reset();

    	if (!mstate->warm) {
		memset(mstate->cp1, 0, sizeof(mstate->cp1[32]));
		memset(mstate->fpr, 0, sizeof(mstate->fpr[32]));
		mstate->count_seed = mstate->now;
		mstate->cp0[PRId] = ImpRev; //Fix me, Shi yang 2006-08-30
		mstate->cp1[FCR0] = ImpRev;
		mstate->nop_count = 0;
    	}
    	mstate->ll_bit = 0;
    	mstate->sync_bit = 0;

    	// Deliver the reset exception.
    	if (mstate->warm)
		deliver_soft_reset(mstate);
    	else
		deliver_cold_reset(mstate);

    	process_reset(mstate);
}

void 
mips_trigger_irq(MIPS_State* mstate)
{
	VA epc;

	//Get the content of the cause register
	UInt32 cause = mstate->cp0[Cause];

	//When the instruction is in the delay slot, we have to delay an instruction 
    	if (!branch_delay_slot(mstate))
		epc = mstate->pc;
    	else {
		epc = mstate->pc - 4;
		cause = set_bit(cause, Cause_BD);
    	}
    	mstate->cp0[Cause] = cause;
	mstate->cp0[EPC] = epc;

	//Change the pointer pc to deal with the interrupt handler
	if(bit(mstate->cp0[SR], SR_BEV) )
	{
		mstate->pc = 0xbfc00380;
	} else {
		mstate->pc = 0x80000180;
	}

	mstate->pipeline = nothing_special;
	
}

static void 
mips_step_once()
{
	mstate->gpr[0] = 0;
	
	/* Check for interrupts. In real hardware, these have a priority lower
	 * than all exceptions, but simulating this effect is too hard to be
	 * worth the effort (interrupts and resets are not meant to be
	 * delivered accurately anyway.)
         */
	if(mstate->irq_pending)
	{
		mips_trigger_irq(mstate);
	}
	
	/* Look up the ITLB. It's not clear from the manuals whether the ITLB
	 * stores the ASIDs or not. I assume it does. ITLB has the same size
	 * as in the real hardware, mapping two 4KB pages.  Because decoding a
	 * MIPS64 virtual address is far from trivial, ITLB and DTLB actually