stm32f10x_rcc.s79

用于监视I2C通信总线

//  708       break;
//  709 
//  710     default:
//  711       RCC_Clocks->SYSCLK_Frequency = HSI_Value;
//  712       break;
//  713   }
//  714 
//  715   /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
//  716   /* Get HCLK prescaler */
//  717   tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
        LDR      R3,[R1, #+0]
        ANDS     R4,R3,#0xF0
//  718   tmp = tmp >> 4;
//  719   presc = APBAHBPrescTable[tmp];
//  720 
//  721   /* HCLK clock frequency */
//  722   RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
        LDR.N    R3,??RCC_GetClocksFreq_0+0x8  ;; APBAHBPrescTable
        LSRS     R4,R4,#+4
        LDRB     R4,[R3, R4]
        LSRS     R2,R2,R4
        STR      R2,[R0, #+4]
//  723 
//  724   /* Get PCLK1 prescaler */
//  725   tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
        LDR      R4,[R1, #+0]
        ANDS     R4,R4,#0x700
//  726   tmp = tmp >> 8;
//  727   presc = APBAHBPrescTable[tmp];
//  728 
//  729   /* PCLK1 clock frequency */
//  730   RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
        LSRS     R4,R4,#+8
        LDRB     R4,[R3, R4]
        LSRS     R2,R2,R4
        STR      R2,[R0, #+8]
//  731 
//  732   /* Get PCLK2 prescaler */
//  733   tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
        LDR      R2,[R1, #+0]
        ANDS     R4,R2,#0x3800
//  734   tmp = tmp >> 11;
//  735   presc = APBAHBPrescTable[tmp];
//  736 
//  737   /* PCLK2 clock frequency */
//  738   RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
        LDR      R2,[R0, #+4]
        LSRS     R4,R4,#+11
        LDRB     R4,[R3, R4]
        LSRS     R2,R2,R4
        STR      R2,[R0, #+12]
//  739 
//  740   /* Get ADCCLK prescaler */
//  741   tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
        LDR      R1,[R1, #+0]
        ANDS     R1,R1,#0xC000
//  742   tmp = tmp >> 14;
//  743   presc = ADCPrescTable[tmp];
//  744 
//  745   /* ADCCLK clock frequency */
//  746   RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
        ADDS     R1,R3,R1, LSR #+14
        LDRB     R1,[R1, #+16]
        UDIV     R1,R2,R1
        STR      R1,[R0, #+16]
//  747 }
        POP      {R4,R5,PC}       ;; return
        Nop      
        DATA
??RCC_GetClocksFreq_0:
        DC32     0x7a1200
        DC32     0x3d0900
        DC32     APBAHBPrescTable
        CFI EndBlock cfiBlock21

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable14:
        DC32     0x40021004
//  748 
//  749 /*******************************************************************************
//  750 * Function Name  : RCC_AHBPeriphClockCmd
//  751 * Description    : Enables or disables the AHB peripheral clock.
//  752 * Input          : - RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
//  753 *                    This parameter can be any combination of the following values:
//  754 *                       - RCC_AHBPeriph_DMA1
//  755 *                       - RCC_AHBPeriph_DMA2
//  756 *                       - RCC_AHBPeriph_SRAM
//  757 *                       - RCC_AHBPeriph_FLITF
//  758 *                       - RCC_AHBPeriph_CRC
//  759 *                       - RCC_AHBPeriph_FSMC
//  760 *                       - RCC_AHBPeriph_SDIO
//  761 *                    SRAM and FLITF clock can be disabled only during sleep mode.
//  762 *                  - NewState: new state of the specified peripheral clock.
//  763 *                    This parameter can be: ENABLE or DISABLE.
//  764 * Output         : None
//  765 * Return         : None
//  766 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock22 Using cfiCommon0
        CFI Function RCC_AHBPeriphClockCmd
        THUMB
//  767 void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
//  768 {
//  769   /* Check the parameters */
//  770   assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
//  771   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  772 
//  773   if (NewState != DISABLE)
RCC_AHBPeriphClockCmd:
        LDR.N    R2,??RCC_AHBPeriphClockCmd_0  ;; 0x40021014
        CMP      R1,#+0
        LDR      R1,[R2, #+0]
        ITTT    NE 
//  774   {
//  775     RCC->AHBENR |= RCC_AHBPeriph;
        ORRNE    R0,R0,R1
        STRNE    R0,[R2, #+0]
        BXNE     LR
//  776   }
//  777   else
//  778   {
//  779     RCC->AHBENR &= ~RCC_AHBPeriph;
        B.N      ?Subroutine2
        DATA
??RCC_AHBPeriphClockCmd_0:
        DC32     0x40021014
        CFI EndBlock cfiBlock22
//  780   }
//  781 }
//  782 
//  783 /*******************************************************************************
//  784 * Function Name  : RCC_APB2PeriphClockCmd
//  785 * Description    : Enables or disables the High Speed APB (APB2) peripheral clock.
//  786 * Input          : - RCC_APB2Periph: specifies the APB2 peripheral to gates its
//  787 *                    clock.
//  788 *                    This parameter can be any combination of the following values:
//  789 *                       - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
//  790 *                         RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
//  791 *                         RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
//  792 *                         RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
//  793 *                         RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
//  794 *                         RCC_APB2Periph_ALL
//  795 *                  - NewState: new state of the specified peripheral clock.
//  796 *                    This parameter can be: ENABLE or DISABLE.
//  797 * Output         : None
//  798 * Return         : None
//  799 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock23 Using cfiCommon0
        CFI Function RCC_APB2PeriphClockCmd
        THUMB
//  800 void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
//  801 {
//  802   /* Check the parameters */
//  803   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
//  804   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  805 
//  806   if (NewState != DISABLE)
RCC_APB2PeriphClockCmd:
        LDR.N    R2,??Subroutine2_0  ;; 0x40021018
        CMP      R1,#+0
        LDR      R1,[R2, #+0]
        ITTT    NE 
//  807   {
//  808     RCC->APB2ENR |= RCC_APB2Periph;
        ORRNE    R0,R0,R1
        STRNE    R0,[R2, #+0]
        BXNE     LR
        Nop      
        CFI EndBlock cfiBlock23
//  809   }
//  810   else
//  811   {
//  812     RCC->APB2ENR &= ~RCC_APB2Periph;
        REQUIRE ?Subroutine2
        ;; // Fall through to label ?Subroutine2
//  813   }
//  814 }

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock24 Using cfiCommon0
        CFI NoFunction
        THUMB
?Subroutine2:
        BICS     R1,R1,R0
        STR      R1,[R2, #+0]
        BX       LR               ;; return
        Nop      
        DATA
??Subroutine2_0:
        DC32     0x40021018
        CFI EndBlock cfiBlock24
//  815 
//  816 /*******************************************************************************
//  817 * Function Name  : RCC_APB1PeriphClockCmd
//  818 * Description    : Enables or disables the Low Speed APB (APB1) peripheral clock.
//  819 * Input          : - RCC_APB1Periph: specifies the APB1 peripheral to gates its
//  820 *                    clock.
//  821 *                    This parameter can be any combination of the following values:
//  822 *                       - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
//  823 *                         RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
//  824 *                         RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
//  825 *                         RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
//  826 *                         RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
//  827 *                         RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,
//  828 *                         RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
//  829 *                  - NewState: new state of the specified peripheral clock.
//  830 *                    This parameter can be: ENABLE or DISABLE.
//  831 * Output         : None
//  832 * Return         : None
//  833 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock25 Using cfiCommon0
        CFI Function RCC_APB1PeriphClockCmd
        THUMB
//  834 void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
//  835 {
//  836   /* Check the parameters */
//  837   assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
//  838   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  839 
//  840   if (NewState != DISABLE)
RCC_APB1PeriphClockCmd:
        LDR.N    R2,??RCC_APB1PeriphClockCmd_0  ;; 0x4002101c
        CMP      R1,#+0
        LDR      R1,[R2, #+0]
        ITTT    NE 
//  841   {
//  842     RCC->APB1ENR |= RCC_APB1Periph;
        ORRNE    R0,R0,R1
        STRNE    R0,[R2, #+0]
        BXNE     LR
//  843   }
//  844   else
//  845   {
//  846     RCC->APB1ENR &= ~RCC_APB1Periph;
        B.N      ?Subroutine2
        DATA
??RCC_APB1PeriphClockCmd_0:
        DC32     0x4002101c
        CFI EndBlock cfiBlock25
//  847   }
//  848 }
//  849 
//  850 /*******************************************************************************
//  851 * Function Name  : RCC_APB2PeriphResetCmd
//  852 * Description    : Forces or releases High Speed APB (APB2) peripheral reset.
//  853 * Input          : - RCC_APB2Periph: specifies the APB2 peripheral to reset.
//  854 *                    This parameter can be any combination of the following values:
//  855 *                       - RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
//  856 *                         RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
//  857 *                         RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
//  858 *                         RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
//  859 *                         RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
//  860 *                         RCC_APB2Periph_ALL
//  861 *                  - NewState: new state of the specified peripheral reset.
//  862 *                    This parameter can be: ENABLE or DISABLE.
//  863 * Output         : None
//  864 * Return         : None
//  865 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock26 Using cfiCommon0
        CFI Function RCC_APB2PeriphResetCmd
        THUMB
//  866 void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
//  867 {
//  868   /* Check the parameters */
//  869   assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
//  870   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  871 
//  872   if (NewState != DISABLE)
RCC_APB2PeriphResetCmd:
        LDR.N    R2,??RCC_APB2PeriphResetCmd_0  ;; 0x4002100c
        CMP      R1,#+0
        LDR      R1,[R2, #+0]
        ITTT    NE 
//  873   {
//  874     RCC->APB2RSTR |= RCC_APB2Periph;
        ORRNE    R0,R0,R1
        STRNE    R0,[R2, #+0]
        BXNE     LR
//  875   }
//  876   else
//  877   {
//  878     RCC->APB2RSTR &= ~RCC_APB2Periph;
        B.N      ?Subroutine2
        DATA
??RCC_APB2PeriphResetCmd_0:
        DC32     0x4002100c
        CFI EndBlock cfiBlock26
//  879   }
//  880 }
//  881 
//  882 /*******************************************************************************
//  883 * Function Name  : RCC_APB1PeriphResetCmd
//  884 * Description    : Forces or releases Low Speed APB (APB1) peripheral reset.
//  885 * Input          : - RCC_APB1Periph: specifies the APB1 peripheral to reset.
//  886 *                    This parameter can be any combination of the following values:
//  887 *                       - RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
//  888 *                         RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
//  889 *                         RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
//  890 *                         RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, 
//  891 *                         RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
//  892 *                         RCC_APB1Periph_USB, RCC_APB1Periph_CAN, RCC_APB1Periph_BKP,
//  893 *                         RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
//  894 *                  - NewState: new state of the specified peripheral clock.
//  895 *                    This parameter can be: ENABLE or DISABLE.
//  896 * Output         : None
//  897 * Return         : None
//  898 ************************************************************************