stm32f10x_rcc.s79

用于监视I2C通信总线

//  521   /* Check the parameters */
//  522   assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
//  523 
//  524   *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
RCC_USBCLKConfig:
        LDR.N    R1,??RCC_USBCLKConfig_0  ;; 0x424200d8
        STR      R0,[R1, #+0]
//  525 }
        BX       LR               ;; return
        Nop      
        DATA
??RCC_USBCLKConfig_0:
        DC32     0x424200d8
        CFI EndBlock cfiBlock14
//  526 
//  527 /*******************************************************************************
//  528 * Function Name  : RCC_ADCCLKConfig
//  529 * Description    : Configures the ADC clock (ADCCLK).
//  530 * Input          : - RCC_PCLK2: defines the ADC clock divider. This clock is
//  531 *                    derived from the APB2 clock (PCLK2).
//  532 *                    This parameter can be one of the following values:
//  533 *                       - RCC_PCLK2_Div2: ADC clock = PCLK2/2
//  534 *                       - RCC_PCLK2_Div4: ADC clock = PCLK2/4
//  535 *                       - RCC_PCLK2_Div6: ADC clock = PCLK2/6
//  536 *                       - RCC_PCLK2_Div8: ADC clock = PCLK2/8
//  537 * Output         : None
//  538 * Return         : None
//  539 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock15 Using cfiCommon0
        CFI Function RCC_ADCCLKConfig
        THUMB
//  540 void RCC_ADCCLKConfig(u32 RCC_PCLK2)
//  541 {
//  542   u32 tmpreg = 0;
//  543 
//  544   /* Check the parameters */
//  545   assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
//  546 
//  547   tmpreg = RCC->CFGR;
RCC_ADCCLKConfig:
        LDR.N    R1,??DataTable14  ;; 0x40021004
//  548 
//  549   /* Clear ADCPRE[1:0] bits */
//  550   tmpreg &= CFGR_ADCPRE_Reset_Mask;
//  551 
//  552   /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
//  553   tmpreg |= RCC_PCLK2;
//  554 
//  555   /* Store the new value */
//  556   RCC->CFGR = tmpreg;
        MVNS     R3,#+49152
        Nop      
        CFI EndBlock cfiBlock15
        REQUIRE ?Subroutine1
        ;; // Fall through to label ?Subroutine1
//  557 }

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock16 Using cfiCommon0
        CFI NoFunction
        THUMB
?Subroutine1:
        LDR      R2,[R1, #+0]
        ANDS     R3,R3,R2
        ORRS     R0,R0,R3
        STR      R0,[R1, #+0]
        BX       LR               ;; return
        CFI EndBlock cfiBlock16
//  558 
//  559 /*******************************************************************************
//  560 * Function Name  : RCC_LSEConfig
//  561 * Description    : Configures the External Low Speed oscillator (LSE).
//  562 * Input          : - RCC_LSE: specifies the new state of the LSE.
//  563 *                    This parameter can be one of the following values:
//  564 *                       - RCC_LSE_OFF: LSE oscillator OFF
//  565 *                       - RCC_LSE_ON: LSE oscillator ON
//  566 *                       - RCC_LSE_Bypass: LSE oscillator bypassed with external
//  567 *                         clock
//  568 * Output         : None
//  569 * Return         : None
//  570 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock17 Using cfiCommon0
        CFI Function RCC_LSEConfig
        THUMB
//  571 void RCC_LSEConfig(u8 RCC_LSE)
//  572 {
//  573   /* Check the parameters */
//  574   assert_param(IS_RCC_LSE(RCC_LSE));
//  575 
//  576   /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
//  577   /* Reset LSEON bit */
//  578   *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
RCC_LSEConfig:
        LDR.N    R1,??DataTable17  ;; 0x40021020
        MOVS     R2,#+0
//  579 
//  580   /* Reset LSEBYP bit */
//  581   *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
//  582 
//  583   /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
//  584   switch(RCC_LSE)
        CMP      R0,#+1
        STRB     R2,[R1, #+0]
        STRB     R2,[R1, #+0]
        BEQ.N    ??RCC_LSEConfig_0
        CMP      R0,#+4
        BEQ.N    ??RCC_LSEConfig_1
        BX       LR
//  585   {
//  586     case RCC_LSE_ON:
//  587       /* Set LSEON bit */
//  588       *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;
//  589       break;
//  590       
//  591     case RCC_LSE_Bypass:
//  592       /* Set LSEBYP and LSEON bits */
//  593       *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
??RCC_LSEConfig_1:
        MOVS     R0,#+5
??RCC_LSEConfig_0:
        STRB     R0,[R1, #+0]
//  594       break;            
//  595       
//  596     default:
//  597       break;      
//  598   }
//  599 }
        BX       LR
        CFI EndBlock cfiBlock17
//  600 
//  601 /*******************************************************************************
//  602 * Function Name  : RCC_LSICmd
//  603 * Description    : Enables or disables the Internal Low Speed oscillator (LSI).
//  604 *                  LSI can not be disabled if the IWDG is running.
//  605 * Input          : - NewState: new state of the LSI.
//  606 *                    This parameter can be: ENABLE or DISABLE.
//  607 * Output         : None
//  608 * Return         : None
//  609 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock18 Using cfiCommon0
        CFI Function RCC_LSICmd
        THUMB
//  610 void RCC_LSICmd(FunctionalState NewState)
//  611 {
//  612   /* Check the parameters */
//  613   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  614 
//  615   *(vu32 *) CSR_LSION_BB = (u32)NewState;
RCC_LSICmd:
        LDR.N    R1,??RCC_LSICmd_0  ;; 0x42420480
        STR      R0,[R1, #+0]
//  616 }
        BX       LR               ;; return
        Nop      
        DATA
??RCC_LSICmd_0:
        DC32     0x42420480
        CFI EndBlock cfiBlock18
//  617 
//  618 /*******************************************************************************
//  619 * Function Name  : RCC_RTCCLKConfig
//  620 * Description    : Configures the RTC clock (RTCCLK).
//  621 *                  Once the RTC clock is selected it can抰 be changed unless the
//  622 *                  Backup domain is reset.
//  623 * Input          : - RCC_RTCCLKSource: specifies the RTC clock source.
//  624 *                    This parameter can be one of the following values:
//  625 *                       - RCC_RTCCLKSource_LSE: LSE selected as RTC clock
//  626 *                       - RCC_RTCCLKSource_LSI: LSI selected as RTC clock
//  627 *                       - RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
//  628 *                         selected as RTC clock
//  629 * Output         : None
//  630 * Return         : None
//  631 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock19 Using cfiCommon0
        CFI Function RCC_RTCCLKConfig
        THUMB
//  632 void RCC_RTCCLKConfig(u32 RCC_RTCCLKSource)
//  633 {
//  634   /* Check the parameters */
//  635   assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
//  636 
//  637   /* Select the RTC clock source */
//  638   RCC->BDCR |= RCC_RTCCLKSource;
RCC_RTCCLKConfig:
        LDR.N    R1,??DataTable17  ;; 0x40021020
        LDR      R2,[R1, #+0]
        B.N      ??Subroutine0_0
        CFI EndBlock cfiBlock19
//  639 }
//  640 
//  641 /*******************************************************************************
//  642 * Function Name  : RCC_RTCCLKCmd
//  643 * Description    : Enables or disables the RTC clock.
//  644 *                  This function must be used only after the RTC clock was
//  645 *                  selected using the RCC_RTCCLKConfig function.
//  646 * Input          : - NewState: new state of the RTC clock.
//  647 *                    This parameter can be: ENABLE or DISABLE.
//  648 * Output         : None
//  649 * Return         : None
//  650 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock20 Using cfiCommon0
        CFI Function RCC_RTCCLKCmd
        THUMB
//  651 void RCC_RTCCLKCmd(FunctionalState NewState)
//  652 {
//  653   /* Check the parameters */
//  654   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  655 
//  656   *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
RCC_RTCCLKCmd:
        LDR.N    R1,??RCC_RTCCLKCmd_0  ;; 0x4242043c
        STR      R0,[R1, #+0]
//  657 }
        BX       LR               ;; return
        Nop      
        DATA
??RCC_RTCCLKCmd_0:
        DC32     0x4242043c
        CFI EndBlock cfiBlock20
//  658 
//  659 /*******************************************************************************
//  660 * Function Name  : RCC_GetClocksFreq
//  661 * Description    : Returns the frequencies of different on chip clocks.
//  662 * Input          : - RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
//  663 *                    will hold the clocks frequencies.
//  664 * Output         : None
//  665 * Return         : None
//  666 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock21 Using cfiCommon0
        CFI Function RCC_GetClocksFreq
        THUMB
//  667 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
//  668 {
//  669   u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
//  670 
//  671   /* Get SYSCLK source -------------------------------------------------------*/
//  672   tmp = RCC->CFGR & CFGR_SWS_Mask;
RCC_GetClocksFreq:
        LDR.N    R1,??DataTable14  ;; 0x40021004
        PUSH     {R4,R5,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R5 Frame(CFA, -8)
        CFI R4 Frame(CFA, -12)
        CFI CFA R13+12
        LDR      R2,[R1, #+0]
        ANDS     R3,R2,#0xC
//  673 
//  674   switch (tmp)
        LDR.N    R2,??RCC_GetClocksFreq_0  ;; 0x7a1200
        CMP      R3,#+8
        BNE.N    ??RCC_GetClocksFreq_1
//  675   {
//  676     case 0x00:  /* HSI used as system clock */
//  677       RCC_Clocks->SYSCLK_Frequency = HSI_Value;
//  678       break;
//  679 
//  680     case 0x04:  /* HSE used as system clock */
//  681       RCC_Clocks->SYSCLK_Frequency = HSE_Value;
//  682       break;
//  683 
//  684     case 0x08:  /* PLL used as system clock */
//  685       /* Get PLL clock source and multiplication factor ----------------------*/
//  686       pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
        LDR      R3,[R1, #+0]
//  687       pllmull = ( pllmull >> 18) + 2;
//  688 
//  689       pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
        LDR      R5,[R1, #+0]
        MOVS     R4,#+65536
        ANDS     R3,R3,#0x3C0000
        LSRS     R3,R3,#+18
        ADDS     R3,R3,#+2
        ANDS     R4,R4,R5
//  690 
//  691       if (pllsource == 0x00)
        BNE.N    ??RCC_GetClocksFreq_2
//  692       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
//  693         RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
??RCC_GetClocksFreq_3:
        MOVS     R2,R3
        LDR.N    R3,??RCC_GetClocksFreq_0+0x4  ;; 0x3d0900
        MULS     R2,R3,R2
        B.N      ??RCC_GetClocksFreq_1
//  694       }
//  695       else
//  696       {/* HSE selected as PLL clock entry */
//  697 
//  698         if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
??RCC_GetClocksFreq_2:
        LDR      R4,[R1, #+0]
        LSLS     R4,R4,#+14
        BMI.N    ??RCC_GetClocksFreq_3
//  699         {/* HSE oscillator clock divided by 2 */
//  700 
//  701           RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
//  702         }
//  703         else
//  704         {
//  705           RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
??RCC_GetClocksFreq_4:
        MULS     R3,R2,R3
        MOVS     R2,R3
??RCC_GetClocksFreq_1:
        STR      R2,[R0, #+0]
//  706         }
//  707       }