📄 stm32f10x_rcc.s79
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// 311 * This parameter can be: ENABLE or DISABLE.
// 312 * Output : None
// 313 * Return : None
// 314 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock6 Using cfiCommon0
CFI Function RCC_PLLCmd
THUMB
// 315 void RCC_PLLCmd(FunctionalState NewState)
// 316 {
// 317 /* Check the parameters */
// 318 assert_param(IS_FUNCTIONAL_STATE(NewState));
// 319
// 320 *(vu32 *) CR_PLLON_BB = (u32)NewState;
RCC_PLLCmd:
LDR.N R1,??RCC_PLLCmd_0 ;; 0x42420060
STR R0,[R1, #+0]
// 321 }
BX LR ;; return
Nop
DATA
??RCC_PLLCmd_0:
DC32 0x42420060
CFI EndBlock cfiBlock6
// 322
// 323 /*******************************************************************************
// 324 * Function Name : RCC_SYSCLKConfig
// 325 * Description : Configures the system clock (SYSCLK).
// 326 * Input : - RCC_SYSCLKSource: specifies the clock source used as system
// 327 * clock. This parameter can be one of the following values:
// 328 * - RCC_SYSCLKSource_HSI: HSI selected as system clock
// 329 * - RCC_SYSCLKSource_HSE: HSE selected as system clock
// 330 * - RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
// 331 * Output : None
// 332 * Return : None
// 333 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock7 Using cfiCommon0
CFI Function RCC_SYSCLKConfig
THUMB
// 334 void RCC_SYSCLKConfig(u32 RCC_SYSCLKSource)
// 335 {
// 336 u32 tmpreg = 0;
// 337
// 338 /* Check the parameters */
// 339 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
// 340
// 341 tmpreg = RCC->CFGR;
RCC_SYSCLKConfig:
LDR.N R1,??DataTable14 ;; 0x40021004
// 342
// 343 /* Clear SW[1:0] bits */
// 344 tmpreg &= CFGR_SW_Mask;
// 345
// 346 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
// 347 tmpreg |= RCC_SYSCLKSource;
// 348
// 349 /* Store the new value */
// 350 RCC->CFGR = tmpreg;
MOVS R3,#+3
B.N ?Subroutine0
CFI EndBlock cfiBlock7
// 351 }
// 352
// 353 /*******************************************************************************
// 354 * Function Name : RCC_GetSYSCLKSource
// 355 * Description : Returns the clock source used as system clock.
// 356 * Input : None
// 357 * Output : None
// 358 * Return : The clock source used as system clock. The returned value can
// 359 * be one of the following:
// 360 * - 0x00: HSI used as system clock
// 361 * - 0x04: HSE used as system clock
// 362 * - 0x08: PLL used as system clock
// 363 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock8 Using cfiCommon0
CFI Function RCC_GetSYSCLKSource
THUMB
// 364 u8 RCC_GetSYSCLKSource(void)
// 365 {
// 366 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
RCC_GetSYSCLKSource:
LDR.N R0,??DataTable14 ;; 0x40021004
LDR R0,[R0, #+0]
ANDS R0,R0,#0xC
BX LR ;; return
CFI EndBlock cfiBlock8
// 367 }
// 368
// 369 /*******************************************************************************
// 370 * Function Name : RCC_HCLKConfig
// 371 * Description : Configures the AHB clock (HCLK).
// 372 * Input : - RCC_SYSCLK: defines the AHB clock divider. This clock is
// 373 * derived from the system clock (SYSCLK).
// 374 * This parameter can be one of the following values:
// 375 * - RCC_SYSCLK_Div1: AHB clock = SYSCLK
// 376 * - RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
// 377 * - RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
// 378 * - RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
// 379 * - RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
// 380 * - RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
// 381 * - RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
// 382 * - RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
// 383 * - RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
// 384 * Output : None
// 385 * Return : None
// 386 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock9 Using cfiCommon0
CFI Function RCC_HCLKConfig
THUMB
// 387 void RCC_HCLKConfig(u32 RCC_SYSCLK)
// 388 {
// 389 u32 tmpreg = 0;
// 390
// 391 /* Check the parameters */
// 392 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
// 393
// 394 tmpreg = RCC->CFGR;
RCC_HCLKConfig:
LDR.N R1,??DataTable14 ;; 0x40021004
// 395
// 396 /* Clear HPRE[3:0] bits */
// 397 tmpreg &= CFGR_HPRE_Reset_Mask;
// 398
// 399 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
// 400 tmpreg |= RCC_SYSCLK;
// 401
// 402 /* Store the new value */
// 403 RCC->CFGR = tmpreg;
MOVS R3,#+240
CFI EndBlock cfiBlock9
REQUIRE ?Subroutine0
;; // Fall through to label ?Subroutine0
// 404 }
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock10 Using cfiCommon0
CFI NoFunction
THUMB
?Subroutine0:
LDR R2,[R1, #+0]
BICS R2,R2,R3
??Subroutine0_0:
ORRS R0,R0,R2
STR R0,[R1, #+0]
BX LR ;; return
CFI EndBlock cfiBlock10
// 405
// 406 /*******************************************************************************
// 407 * Function Name : RCC_PCLK1Config
// 408 * Description : Configures the Low Speed APB clock (PCLK1).
// 409 * Input : - RCC_HCLK: defines the APB1 clock divider. This clock is
// 410 * derived from the AHB clock (HCLK).
// 411 * This parameter can be one of the following values:
// 412 * - RCC_HCLK_Div1: APB1 clock = HCLK
// 413 * - RCC_HCLK_Div2: APB1 clock = HCLK/2
// 414 * - RCC_HCLK_Div4: APB1 clock = HCLK/4
// 415 * - RCC_HCLK_Div8: APB1 clock = HCLK/8
// 416 * - RCC_HCLK_Div16: APB1 clock = HCLK/16
// 417 * Output : None
// 418 * Return : None
// 419 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock11 Using cfiCommon0
CFI Function RCC_PCLK1Config
THUMB
// 420 void RCC_PCLK1Config(u32 RCC_HCLK)
// 421 {
// 422 u32 tmpreg = 0;
// 423
// 424 /* Check the parameters */
// 425 assert_param(IS_RCC_PCLK(RCC_HCLK));
// 426
// 427 tmpreg = RCC->CFGR;
RCC_PCLK1Config:
LDR.N R1,??DataTable14 ;; 0x40021004
// 428
// 429 /* Clear PPRE1[2:0] bits */
// 430 tmpreg &= CFGR_PPRE1_Reset_Mask;
// 431
// 432 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
// 433 tmpreg |= RCC_HCLK;
// 434
// 435 /* Store the new value */
// 436 RCC->CFGR = tmpreg;
MVNS R3,#+1792
B.N ?Subroutine1
CFI EndBlock cfiBlock11
// 437 }
// 438
// 439 /*******************************************************************************
// 440 * Function Name : RCC_PCLK2Config
// 441 * Description : Configures the High Speed APB clock (PCLK2).
// 442 * Input : - RCC_HCLK: defines the APB2 clock divider. This clock is
// 443 * derived from the AHB clock (HCLK).
// 444 * This parameter can be one of the following values:
// 445 * - RCC_HCLK_Div1: APB2 clock = HCLK
// 446 * - RCC_HCLK_Div2: APB2 clock = HCLK/2
// 447 * - RCC_HCLK_Div4: APB2 clock = HCLK/4
// 448 * - RCC_HCLK_Div8: APB2 clock = HCLK/8
// 449 * - RCC_HCLK_Div16: APB2 clock = HCLK/16
// 450 * Output : None
// 451 * Return : None
// 452 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock12 Using cfiCommon0
CFI Function RCC_PCLK2Config
THUMB
// 453 void RCC_PCLK2Config(u32 RCC_HCLK)
// 454 {
// 455 u32 tmpreg = 0;
// 456
// 457 /* Check the parameters */
// 458 assert_param(IS_RCC_PCLK(RCC_HCLK));
// 459
// 460 tmpreg = RCC->CFGR;
RCC_PCLK2Config:
LDR.N R1,??DataTable14 ;; 0x40021004
// 461
// 462 /* Clear PPRE2[2:0] bits */
// 463 tmpreg &= CFGR_PPRE2_Reset_Mask;
// 464
// 465 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
// 466 tmpreg |= RCC_HCLK << 3;
// 467
// 468 /* Store the new value */
// 469 RCC->CFGR = tmpreg;
MVNS R3,#+14336
LDR R2,[R1, #+0]
ANDS R3,R3,R2
ORRS R0,R3,R0, LSL #+3
STR R0,[R1, #+0]
// 470 }
BX LR ;; return
CFI EndBlock cfiBlock12
// 471
// 472 /*******************************************************************************
// 473 * Function Name : RCC_ITConfig
// 474 * Description : Enables or disables the specified RCC interrupts.
// 475 * Input : - RCC_IT: specifies the RCC interrupt sources to be enabled
// 476 * or disabled.
// 477 * This parameter can be any combination of the following values:
// 478 * - RCC_IT_LSIRDY: LSI ready interrupt
// 479 * - RCC_IT_LSERDY: LSE ready interrupt
// 480 * - RCC_IT_HSIRDY: HSI ready interrupt
// 481 * - RCC_IT_HSERDY: HSE ready interrupt
// 482 * - RCC_IT_PLLRDY: PLL ready interrupt
// 483 * - NewState: new state of the specified RCC interrupts.
// 484 * This parameter can be: ENABLE or DISABLE.
// 485 * Output : None
// 486 * Return : None
// 487 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock13 Using cfiCommon0
CFI Function RCC_ITConfig
THUMB
// 488 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
// 489 {
// 490 /* Check the parameters */
// 491 assert_param(IS_RCC_IT(RCC_IT));
// 492 assert_param(IS_FUNCTIONAL_STATE(NewState));
// 493
// 494 if (NewState != DISABLE)
RCC_ITConfig:
LDR.N R2,??RCC_ITConfig_0 ;; 0x40021009
CMP R1,#+0
LDRB R1,[R2, #+0]
ITTT NE
// 495 {
// 496 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
// 497 *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;
ORRNE R0,R0,R1
STRBNE R0,[R2, #+0]
BXNE LR
// 498 }
// 499 else
// 500 {
// 501 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
// 502 *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;
BICS R1,R1,R0
STRB R1,[R2, #+0]
// 503 }
// 504 }
BX LR ;; return
DATA
??RCC_ITConfig_0:
DC32 0x40021009
CFI EndBlock cfiBlock13
// 505
// 506 /*******************************************************************************
// 507 * Function Name : RCC_USBCLKConfig
// 508 * Description : Configures the USB clock (USBCLK).
// 509 * Input : - RCC_USBCLKSource: specifies the USB clock source. This clock
// 510 * is derived from the PLL output.
// 511 * This parameter can be one of the following values:
// 512 * - RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5
// 513 * selected as USB clock source
// 514 * - RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB
// 515 * clock source
// 516 * Output : None
// 517 * Return : None
// 518 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock14 Using cfiCommon0
CFI Function RCC_USBCLKConfig
THUMB
// 519 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
// 520 {
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