stm32f10x_rcc.s79

用于监视I2C通信总线

        STR      R3,[R1, #+0]
//  132   
//  133   /* Reset HSEON, CSSON and PLLON bits */
//  134   RCC->CR &= (u32)0xFEF6FFFF;
        LDR      R2,[R0, #+0]
        LDR.N    R3,??RCC_DeInit_0+0x4  ;; 0xfffffffffef6ffff
        ANDS     R3,R3,R2
        STR      R3,[R0, #+0]
//  135 
//  136   /* Reset HSEBYP bit */
//  137   RCC->CR &= (u32)0xFFFBFFFF;
        LDR      R2,[R0, #+0]
        MVNS     R3,#+262144
        ANDS     R3,R3,R2
        STR      R3,[R0, #+0]
//  138 
//  139   /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
//  140   RCC->CFGR &= (u32)0xFF80FFFF;
        LDR      R0,[R1, #+0]
        MVNS     R2,#+8323072
        ANDS     R2,R2,R0
//  141 
//  142   /* Disable all interrupts */
//  143   RCC->CIR = 0x00000000;
        LDR.N    R0,??DataTable19  ;; 0x40021008
        STR      R2,[R1, #+0]
        MOVS     R1,#+0
        STR      R1,[R0, #+0]
//  144 }
        BX       LR               ;; return
        DATA
??RCC_DeInit_0:
        DC32     0xfffffffff8ff0000
        DC32     0xfffffffffef6ffff
        CFI EndBlock cfiBlock0
//  145 
//  146 /*******************************************************************************
//  147 * Function Name  : RCC_HSEConfig
//  148 * Description    : Configures the External High Speed oscillator (HSE).
//  149 *                  HSE can not be stopped if it is used directly or through the 
//  150 *                  PLL as system clock.
//  151 * Input          : - RCC_HSE: specifies the new state of the HSE.
//  152 *                    This parameter can be one of the following values:
//  153 *                       - RCC_HSE_OFF: HSE oscillator OFF
//  154 *                       - RCC_HSE_ON: HSE oscillator ON
//  155 *                       - RCC_HSE_Bypass: HSE oscillator bypassed with external
//  156 *                         clock
//  157 * Output         : None
//  158 * Return         : None
//  159 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock1 Using cfiCommon0
        CFI Function RCC_HSEConfig
        THUMB
//  160 void RCC_HSEConfig(u32 RCC_HSE)
//  161 {
//  162   /* Check the parameters */
//  163   assert_param(IS_RCC_HSE(RCC_HSE));
//  164 
//  165   /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
//  166   /* Reset HSEON bit */
//  167   RCC->CR &= CR_HSEON_Reset;
RCC_HSEConfig:
        LDR.N    R1,??DataTable15  ;; 0x40021000
        MVNS     R3,#+65536
        LDR      R2,[R1, #+0]
        ANDS     R3,R3,R2
        STR      R3,[R1, #+0]
//  168 
//  169   /* Reset HSEBYP bit */
//  170   RCC->CR &= CR_HSEBYP_Reset;
        LDR      R2,[R1, #+0]
        MVNS     R3,#+262144
        ANDS     R3,R3,R2
        STR      R3,[R1, #+0]
//  171 
//  172   /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
//  173   switch(RCC_HSE)
        MOVS     R2,#+65536
        CMP      R0,R2
        BEQ.N    ??RCC_HSEConfig_0
        LSLS     R2,R2,#+2
        CMP      R0,R2
        BEQ.N    ??RCC_HSEConfig_1
        BX       LR
//  174   {
//  175     case RCC_HSE_ON:
//  176       /* Set HSEON bit */
//  177       RCC->CR |= CR_HSEON_Set;
??RCC_HSEConfig_0:
        LDR      R0,[R1, #+0]
        ORRS     R0,R0,#0x10000
        B.N      ??RCC_HSEConfig_2
//  178       break;
//  179       
//  180     case RCC_HSE_Bypass:
//  181       /* Set HSEBYP and HSEON bits */
//  182       RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
??RCC_HSEConfig_1:
        LDR      R0,[R1, #+0]
        ORRS     R0,R0,#0x50000
??RCC_HSEConfig_2:
        STR      R0,[R1, #+0]
//  183       break;            
//  184       
//  185     default:
//  186       break;      
//  187   }
//  188 }
        BX       LR
        CFI EndBlock cfiBlock1
//  189 
//  190 /*******************************************************************************
//  191 * Function Name  : RCC_WaitForHSEStartUp
//  192 * Description    : Waits for HSE start-up.
//  193 * Input          : None
//  194 * Output         : None
//  195 * Return         : An ErrorStatus enumuration value:
//  196 *                         - SUCCESS: HSE oscillator is stable and ready to use
//  197 *                         - ERROR: HSE oscillator not yet ready
//  198 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock2 Using cfiCommon0
        CFI Function RCC_WaitForHSEStartUp
        THUMB
//  199 ErrorStatus RCC_WaitForHSEStartUp(void)
//  200 {
RCC_WaitForHSEStartUp:
        PUSH     {R4,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R4 Frame(CFA, -8)
        CFI CFA R13+8
//  201   ErrorStatus status = ERROR;
        LDR.N    R4,??RCC_WaitForHSEStartUp_0  ;; HSEStatus
//  202 
//  203   /* Wait till HSE is ready and if Time out is reached exit */
//  204   do
//  205   {
//  206     HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
??RCC_WaitForHSEStartUp_1:
        MOVS     R0,#+49
        BL       RCC_GetFlagStatus
        STRB     R0,[R4, #+0]
//  207     StartUpCounter++;  
        LDR      R0,[R4, #+4]
        ADDS     R0,R0,#+1
        STR      R0,[R4, #+4]
//  208   } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
        LDRB     R0,[R4, #+0]
        CBNZ     R0,??RCC_WaitForHSEStartUp_2
        LDR      R0,[R4, #+4]
        LDR.N    R1,??RCC_WaitForHSEStartUp_0+0x4  ;; 0x1ff
        CMP      R0,R1
        BNE.N    ??RCC_WaitForHSEStartUp_1
//  209 
//  210 
//  211   if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
??RCC_WaitForHSEStartUp_2:
        MOVS     R0,#+49
        BL       RCC_GetFlagStatus
        CBZ      R0,??RCC_WaitForHSEStartUp_3
//  212   {
//  213     status = SUCCESS;
        MOVS     R0,#+1
//  214   }
//  215   else
//  216   {
//  217     status = ERROR;
//  218   }  
//  219 
//  220   return (status);
??RCC_WaitForHSEStartUp_3:
        POP      {R4,PC}          ;; return
        Nop      
        DATA
??RCC_WaitForHSEStartUp_0:
        DC32     HSEStatus
        DC32     0x1ff
        CFI EndBlock cfiBlock2
//  221 }
//  222 
//  223 /*******************************************************************************
//  224 * Function Name  : RCC_AdjustHSICalibrationValue
//  225 * Description    : Adjusts the Internal High Speed oscillator (HSI) calibration
//  226 *                  value.
//  227 * Input          : - HSICalibrationValue: specifies the calibration trimming value.
//  228 *                    This parameter must be a number between 0 and 0x1F.
//  229 * Output         : None
//  230 * Return         : None
//  231 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock3 Using cfiCommon0
        CFI Function RCC_AdjustHSICalibrationValue
        THUMB
//  232 void RCC_AdjustHSICalibrationValue(u8 HSICalibrationValue)
//  233 {
//  234   u32 tmpreg = 0;
//  235 
//  236   /* Check the parameters */
//  237   assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
//  238 
//  239   tmpreg = RCC->CR;
RCC_AdjustHSICalibrationValue:
        LDR.N    R1,??DataTable15  ;; 0x40021000
//  240 
//  241   /* Clear HSITRIM[4:0] bits */
//  242   tmpreg &= CR_HSITRIM_Mask;
//  243 
//  244   /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
//  245   tmpreg |= (u32)HSICalibrationValue << 3;
//  246 
//  247   /* Store the new value */
//  248   RCC->CR = tmpreg;
        MOVS     R3,#+248
        LDR      R2,[R1, #+0]
        BICS     R2,R2,R3
        ORRS     R0,R2,R0, LSL #+3
        STR      R0,[R1, #+0]
//  249 }
        BX       LR               ;; return
        CFI EndBlock cfiBlock3
//  250 
//  251 /*******************************************************************************
//  252 * Function Name  : RCC_HSICmd
//  253 * Description    : Enables or disables the Internal High Speed oscillator (HSI).
//  254 *                  HSI can not be stopped if it is used directly or through the 
//  255 *                  PLL as system clock.
//  256 * Input          : - NewState: new state of the HSI.
//  257 *                    This parameter can be: ENABLE or DISABLE.
//  258 * Output         : None
//  259 * Return         : None
//  260 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock4 Using cfiCommon0
        CFI Function RCC_HSICmd
        THUMB
//  261 void RCC_HSICmd(FunctionalState NewState)
//  262 {
//  263   /* Check the parameters */
//  264   assert_param(IS_FUNCTIONAL_STATE(NewState));
//  265 
//  266   *(vu32 *) CR_HSION_BB = (u32)NewState;
RCC_HSICmd:
        LDR.N    R1,??RCC_HSICmd_0  ;; 0x42420000
        STR      R0,[R1, #+0]
//  267 }
        BX       LR               ;; return
        Nop      
        DATA
??RCC_HSICmd_0:
        DC32     0x42420000
        CFI EndBlock cfiBlock4
//  268 
//  269 /*******************************************************************************
//  270 * Function Name  : RCC_PLLConfig
//  271 * Description    : Configures the PLL clock source and multiplication factor.
//  272 *                  This function must be used only when the PLL is disabled.
//  273 * Input          : - RCC_PLLSource: specifies the PLL entry clock source.
//  274 *                    This parameter can be one of the following values:
//  275 *                       - RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
//  276 *                         by 2 selected as PLL clock entry
//  277 *                       - RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
//  278 *                         as PLL clock entry
//  279 *                       - RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
//  280 *                         by 2 selected as PLL clock entry
//  281 *                  - RCC_PLLMul: specifies the PLL multiplication factor.
//  282 *                    This parameter can be RCC_PLLMul_x where x:[2,16]
//  283 * Output         : None
//  284 * Return         : None
//  285 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock5 Using cfiCommon0
        CFI Function RCC_PLLConfig
        THUMB
//  286 void RCC_PLLConfig(u32 RCC_PLLSource, u32 RCC_PLLMul)
//  287 {
//  288   u32 tmpreg = 0;
//  289 
//  290   /* Check the parameters */
//  291   assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
//  292   assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
//  293 
//  294   tmpreg = RCC->CFGR;
RCC_PLLConfig:
        LDR.N    R2,??DataTable14  ;; 0x40021004
        PUSH     {R4,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R4 Frame(CFA, -8)
        CFI CFA R13+8
//  295 
//  296   /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
//  297   tmpreg &= CFGR_PLL_Mask;
//  298 
//  299   /* Set the PLL configuration bits */
//  300   tmpreg |= RCC_PLLSource | RCC_PLLMul;
//  301 
//  302   /* Store the new value */
//  303   RCC->CFGR = tmpreg;
        MVNS     R4,#+4128768
        LDR      R3,[R2, #+0]
        ANDS     R4,R4,R3
        ORRS     R0,R0,R4
        ORRS     R1,R1,R0
        STR      R1,[R2, #+0]
//  304 }
        POP      {R4,PC}          ;; return
        CFI EndBlock cfiBlock5
//  305 
//  306 /*******************************************************************************
//  307 * Function Name  : RCC_PLLCmd
//  308 * Description    : Enables or disables the PLL.
//  309 *                  The PLL can not be disabled if it is used as system clock.
//  310 * Input          : - NewState: new state of the PLL.