📄 stm32f10x_rcc.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32 EVALUATION 10/Nov/2008 11:44:03 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = thumb /
// Endian = little /
// Stack alignment = 4 /
// Source file = D:\资料\ST\ST\usb\FWLib\library\src\stm32f10x_rcc.c /
// Command line = D:\资料\ST\ST\usb\FWLib\library\src\stm32f10x_rcc.c /
// -D VECT_TAB_FLASH -D USE_STM3210E_EVAL -lA /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\STM3210E-EVAL\List\ -o /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\STM3210E-EVAL\Obj\ -z9 --debug /
// --cpu_mode thumb --endian little --cpu cortex-M3 /
// --stack_align 4 --require_prototypes --fpu None /
// --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench 4.0 /
// Evaluation\arm\LIB\dl7mptnnl8f.h" -I /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\..\..\include\ -I /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\..\..\..\..\library\inc\ -I /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\..\..\..\..\..\FWLib\library\inc\ -I /
// "C:\Program Files\IAR Systems\Embedded Workbench /
// 4.0 Evaluation\arm\INC\" --inline_threshold=2 /
// List file = D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\STM3210E-EVAL\List\stm32f10x_rcc.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME stm32f10x_rcc
RTMODEL "StackAlign4", "USED"
RTMODEL "__cpu_mode", "__pcs__thumb"
RTMODEL "__data_model", "absolute"
RTMODEL "__endian", "little"
RTMODEL "__rt_version", "6"
RSEG CSTACK:DATA:NOROOT(2)
??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable10 EQU 0
??DataTable11 EQU 0
??DataTable12 EQU 0
??DataTable13 EQU 0
??DataTable16 EQU 0
??DataTable2 EQU 0
??DataTable3 EQU 0
??DataTable4 EQU 0
??DataTable5 EQU 0
??DataTable6 EQU 0
??DataTable7 EQU 0
??DataTable8 EQU 0
??DataTable9 EQU 0
PUBWEAK ?init?tab?DATA_Z
PUBLIC RCC_ADCCLKConfig
FUNCTION RCC_ADCCLKConfig,0203H
PUBLIC RCC_AHBPeriphClockCmd
FUNCTION RCC_AHBPeriphClockCmd,0203H
PUBLIC RCC_APB1PeriphClockCmd
FUNCTION RCC_APB1PeriphClockCmd,0203H
PUBLIC RCC_APB1PeriphResetCmd
FUNCTION RCC_APB1PeriphResetCmd,0203H
PUBLIC RCC_APB2PeriphClockCmd
FUNCTION RCC_APB2PeriphClockCmd,0203H
PUBLIC RCC_APB2PeriphResetCmd
FUNCTION RCC_APB2PeriphResetCmd,0203H
PUBLIC RCC_AdjustHSICalibrationValue
FUNCTION RCC_AdjustHSICalibrationValue,0203H
PUBLIC RCC_BackupResetCmd
FUNCTION RCC_BackupResetCmd,0203H
PUBLIC RCC_ClearFlag
FUNCTION RCC_ClearFlag,0203H
PUBLIC RCC_ClearITPendingBit
FUNCTION RCC_ClearITPendingBit,0203H
PUBLIC RCC_ClockSecuritySystemCmd
FUNCTION RCC_ClockSecuritySystemCmd,0203H
PUBLIC RCC_DeInit
FUNCTION RCC_DeInit,0203H
PUBLIC RCC_GetClocksFreq
FUNCTION RCC_GetClocksFreq,0203H
LOCFRAME CSTACK, 12, STACK
PUBLIC RCC_GetFlagStatus
FUNCTION RCC_GetFlagStatus,0203H
PUBLIC RCC_GetITStatus
FUNCTION RCC_GetITStatus,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC RCC_GetSYSCLKSource
FUNCTION RCC_GetSYSCLKSource,0203H
PUBLIC RCC_HCLKConfig
FUNCTION RCC_HCLKConfig,0203H
PUBLIC RCC_HSEConfig
FUNCTION RCC_HSEConfig,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC RCC_HSICmd
FUNCTION RCC_HSICmd,0203H
PUBLIC RCC_ITConfig
FUNCTION RCC_ITConfig,0203H
PUBLIC RCC_LSEConfig
FUNCTION RCC_LSEConfig,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC RCC_LSICmd
FUNCTION RCC_LSICmd,0203H
PUBLIC RCC_MCOConfig
FUNCTION RCC_MCOConfig,0203H
PUBLIC RCC_PCLK1Config
FUNCTION RCC_PCLK1Config,0203H
PUBLIC RCC_PCLK2Config
FUNCTION RCC_PCLK2Config,0203H
PUBLIC RCC_PLLCmd
FUNCTION RCC_PLLCmd,0203H
PUBLIC RCC_PLLConfig
FUNCTION RCC_PLLConfig,0203H
LOCFRAME CSTACK, 8, STACK
PUBLIC RCC_RTCCLKCmd
FUNCTION RCC_RTCCLKCmd,0203H
PUBLIC RCC_RTCCLKConfig
FUNCTION RCC_RTCCLKConfig,0203H
PUBLIC RCC_SYSCLKConfig
FUNCTION RCC_SYSCLKConfig,0203H
PUBLIC RCC_USBCLKConfig
FUNCTION RCC_USBCLKConfig,0203H
PUBLIC RCC_WaitForHSEStartUp
FUNCTION RCC_WaitForHSEStartUp,0203H
LOCFRAME CSTACK, 8, STACK
CFI Names cfiNames0
CFI StackFrame CFA R13 HUGEDATA
CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, R13:32, R14:32
CFI VirtualResource ?RET:32
CFI EndNames cfiNames0
CFI Common cfiCommon0 Using cfiNames0
CFI CodeAlign 2
CFI DataAlign 4
CFI ReturnAddress ?RET CODE
CFI CFA R13+0
CFI R0 Undefined
CFI R1 Undefined
CFI R2 Undefined
CFI R3 Undefined
CFI R4 SameValue
CFI R5 SameValue
CFI R6 SameValue
CFI R7 SameValue
CFI R8 SameValue
CFI R9 SameValue
CFI R10 SameValue
CFI R11 SameValue
CFI R12 Undefined
CFI R14 Undefined
CFI ?RET R14
CFI EndCommon cfiCommon0
// D:\资料\ST\ST\usb\FWLib\library\src\stm32f10x_rcc.c
// 1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
// 2 * File Name : stm32f10x_rcc.c
// 3 * Author : MCD Application Team
// 4 * Version : V2.0.1
// 5 * Date : 06/13/2008
// 6 * Description : This file provides all the RCC firmware functions.
// 7 ********************************************************************************
// 8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
// 9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
// 10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
// 11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
// 12 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
// 13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
// 14 *******************************************************************************/
// 15
// 16 /* Includes ------------------------------------------------------------------*/
// 17 #include "stm32f10x_rcc.h"
// 18
// 19 /* Private typedef -----------------------------------------------------------*/
// 20 /* Private define ------------------------------------------------------------*/
// 21 /* ------------ RCC registers bit address in the alias region ----------- */
// 22 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
// 23
// 24 /* --- CR Register ---*/
// 25 /* Alias word address of HSION bit */
// 26 #define CR_OFFSET (RCC_OFFSET + 0x00)
// 27 #define HSION_BitNumber 0x00
// 28 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
// 29
// 30 /* Alias word address of PLLON bit */
// 31 #define PLLON_BitNumber 0x18
// 32 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
// 33
// 34 /* Alias word address of CSSON bit */
// 35 #define CSSON_BitNumber 0x13
// 36 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
// 37
// 38 /* --- CFGR Register ---*/
// 39 /* Alias word address of USBPRE bit */
// 40 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
// 41 #define USBPRE_BitNumber 0x16
// 42 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
// 43
// 44 /* --- BDCR Register ---*/
// 45 /* Alias word address of RTCEN bit */
// 46 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
// 47 #define RTCEN_BitNumber 0x0F
// 48 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
// 49
// 50 /* Alias word address of BDRST bit */
// 51 #define BDRST_BitNumber 0x10
// 52 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
// 53
// 54 /* --- CSR Register ---*/
// 55 /* Alias word address of LSION bit */
// 56 #define CSR_OFFSET (RCC_OFFSET + 0x24)
// 57 #define LSION_BitNumber 0x00
// 58 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
// 59
// 60 /* ---------------------- RCC registers bit mask ------------------------ */
// 61 /* CR register bit mask */
// 62 #define CR_HSEBYP_Reset ((u32)0xFFFBFFFF)
// 63 #define CR_HSEBYP_Set ((u32)0x00040000)
// 64 #define CR_HSEON_Reset ((u32)0xFFFEFFFF)
// 65 #define CR_HSEON_Set ((u32)0x00010000)
// 66 #define CR_HSITRIM_Mask ((u32)0xFFFFFF07)
// 67
// 68 /* CFGR register bit mask */
// 69 #define CFGR_PLL_Mask ((u32)0xFFC0FFFF)
// 70 #define CFGR_PLLMull_Mask ((u32)0x003C0000)
// 71 #define CFGR_PLLSRC_Mask ((u32)0x00010000)
// 72 #define CFGR_PLLXTPRE_Mask ((u32)0x00020000)
// 73 #define CFGR_SWS_Mask ((u32)0x0000000C)
// 74 #define CFGR_SW_Mask ((u32)0xFFFFFFFC)
// 75 #define CFGR_HPRE_Reset_Mask ((u32)0xFFFFFF0F)
// 76 #define CFGR_HPRE_Set_Mask ((u32)0x000000F0)
// 77 #define CFGR_PPRE1_Reset_Mask ((u32)0xFFFFF8FF)
// 78 #define CFGR_PPRE1_Set_Mask ((u32)0x00000700)
// 79 #define CFGR_PPRE2_Reset_Mask ((u32)0xFFFFC7FF)
// 80 #define CFGR_PPRE2_Set_Mask ((u32)0x00003800)
// 81 #define CFGR_ADCPRE_Reset_Mask ((u32)0xFFFF3FFF)
// 82 #define CFGR_ADCPRE_Set_Mask ((u32)0x0000C000)
// 83
// 84 /* CSR register bit mask */
// 85 #define CSR_RMVF_Set ((u32)0x01000000)
// 86
// 87 /* RCC Flag Mask */
// 88 #define FLAG_Mask ((u8)0x1F)
// 89
// 90 /* Typical Value of the HSI in Hz */
// 91 #define HSI_Value ((u32)8000000)
// 92
// 93 /* CIR register byte 2 (Bits[15:8]) base address */
// 94 #define CIR_BYTE2_ADDRESS ((u32)0x40021009)
// 95 /* CIR register byte 3 (Bits[23:16]) base address */
// 96 #define CIR_BYTE3_ADDRESS ((u32)0x4002100A)
// 97
// 98 /* CFGR register byte 4 (Bits[31:24]) base address */
// 99 #define CFGR_BYTE4_ADDRESS ((u32)0x40021007)
// 100
// 101 /* BDCR register base address */
// 102 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
// 103
// 104 /* Time out for HSE start up */
// 105 #define HSEStartUp_TimeOut ((u16)0x01FF)
// 106
// 107 /* Private macro -------------------------------------------------------------*/
// 108 /* Private variables ---------------------------------------------------------*/
RSEG DATA_C:CONST:SORT:NOROOT(2)
// 109 static uc8 APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
APBAHBPrescTable:
DATA
DC8 0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9
DC8 2, 4, 6, 8
// 110 static uc8 ADCPrescTable[4] = {2, 4, 6, 8};
// 111
RSEG DATA_Z:DATA:SORT:NOROOT(2)
// 112 static volatile FlagStatus HSEStatus;
HSEStatus:
DS8 1
DS8 3
DS8 4
// 113 static vu32 StartUpCounter = 0;
// 114
// 115 /* Private function prototypes -----------------------------------------------*/
// 116 /* Private functions ---------------------------------------------------------*/
// 117
// 118 /*******************************************************************************
// 119 * Function Name : RCC_DeInit
// 120 * Description : Resets the RCC clock configuration to the default reset state.
// 121 * Input : None
// 122 * Output : None
// 123 * Return : None
// 124 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock0 Using cfiCommon0
CFI Function RCC_DeInit
THUMB
// 125 void RCC_DeInit(void)
// 126 {
// 127 /* Set HSION bit */
// 128 RCC->CR |= (u32)0x00000001;
RCC_DeInit:
LDR.N R0,??DataTable15 ;; 0x40021000
// 129
// 130 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
// 131 RCC->CFGR &= (u32)0xF8FF0000;
LDR.N R3,??RCC_DeInit_0 ;; 0xfffffffff8ff0000
LDR R1,[R0, #+0]
ORRS R1,R1,#0x1
STR R1,[R0, #+0]
LDR.N R1,??DataTable14 ;; 0x40021004
LDR R2,[R1, #+0]
ANDS R3,R3,R2
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