stm32f10x_usart.s79

用于监视I2C通信总线

        MOVS     R1,#+0
        MOVS     R0,#+262144
??USART_DeInit_6:
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
        POP      {PC}
//  110       break;
//  111     
//  112     case UART4_BASE:
//  113       RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
??USART_DeInit_3:
        MOVS     R1,#+1
        LSLS     R0,R1,#+19
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  114       RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
        MOVS     R1,#+0
        MOVS     R0,#+524288
        B.N      ??USART_DeInit_6
//  115       break;
//  116     
//  117     case UART5_BASE:
//  118       RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
??USART_DeInit_4:
        MOVS     R1,#+1
        LSLS     R0,R1,#+20
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  119       RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
        MOVS     R1,#+0
        MOVS     R0,#+1048576
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  120       break;            
//  121 
//  122     default:
//  123       break;
//  124   }
//  125 }
??USART_DeInit_5:
        POP      {PC}             ;; return
        DATA
??USART_DeInit_0:
        DC32     0x40004400
        DC32     0x40004800
        DC32     0x40004c00
        DC32     0x40005000
        CFI EndBlock cfiBlock0
//  126 
//  127 /*******************************************************************************
//  128 * Function Name  : USART_Init
//  129 * Description    : Initializes the USARTx peripheral according to the specified
//  130 *                  parameters in the USART_InitStruct .
//  131 * Input          : - USARTx: Select the USART or the UART peripheral. 
//  132 *                    This parameter can be one of the following values:
//  133 *                     - USART1, USART2, USART3, UART4 or UART5.
//  134 *                  - USART_InitStruct: pointer to a USART_InitTypeDef structure
//  135 *                    that contains the configuration information for the
//  136 *                    specified USART peripheral.
//  137 * Output         : None
//  138 * Return         : None
//  139 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock1 Using cfiCommon0
        CFI Function USART_Init
        THUMB
//  140 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
//  141 {
USART_Init:
        PUSH     {R4,R5,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R5 Frame(CFA, -8)
        CFI R4 Frame(CFA, -12)
        CFI CFA R13+12
        SUB      SP,SP,#+20
        CFI CFA R13+32
        MOVS     R4,R0
//  142   u32 tmpreg = 0x00, apbclock = 0x00;
//  143   u32 integerdivider = 0x00;
//  144   u32 fractionaldivider = 0x00;
//  145   u32 usartxbase = 0;
//  146   RCC_ClocksTypeDef RCC_ClocksStatus;
//  147 
//  148   /* Check the parameters */
//  149   assert_param(IS_USART_ALL_PERIPH(USARTx));
//  150   assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
//  151   assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
//  152   assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
//  153   assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
//  154   assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
//  155   assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
//  156   /* The hardware flow control is available only for USART1, USART2 and USART3 */          
//  157   assert_param(IS_USART_PERIPH_HFC(USARTx, USART_InitStruct->USART_HardwareFlowControl));
//  158   
//  159   usartxbase = (*(u32*)&USARTx);
//  160 
//  161 /*---------------------------- USART CR2 Configuration -----------------------*/
//  162   tmpreg = USARTx->CR2;
        LDRH     R0,[R4, #+16]
        MOVS     R5,R1
//  163   /* Clear STOP[13:12] bits */
//  164   tmpreg &= CR2_STOP_CLEAR_Mask;
//  165 
//  166   /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
//  167   /* Set STOP[13:12] bits according to USART_StopBits value */
//  168   tmpreg |= (u32)USART_InitStruct->USART_StopBits;
//  169   
//  170   /* Write to USART CR2 */
//  171   USARTx->CR2 = (u16)tmpreg;
        LDR.N    R1,??USART_Init_0  ;; 0xcfff
        ANDS     R1,R1,R0
        LDRH     R0,[R5, #+6]
        ORRS     R0,R0,R1
//  172 
//  173 /*---------------------------- USART CR1 Configuration -----------------------*/
//  174   tmpreg = USARTx->CR1;
//  175   /* Clear M, PCE, PS, TE and RE bits */
//  176   tmpreg &= CR1_CLEAR_Mask;
//  177 
//  178   /* Configure the USART Word Length, Parity and mode ----------------------- */
//  179   /* Set the M bits according to USART_WordLength value */
//  180   /* Set PCE and PS bits according to USART_Parity value */
//  181   /* Set TE and RE bits according to USART_Mode value */
//  182   tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
//  183             USART_InitStruct->USART_Mode;
//  184 
//  185   /* Write to USART CR1 */
//  186   USARTx->CR1 = (u16)tmpreg;
        LDR.N    R1,??USART_Init_0+0x4  ;; 0xe9f3
        STRH     R0,[R4, #+16]
        LDRH     R0,[R4, #+12]
        ANDS     R1,R1,R0
        LDRH     R0,[R5, #+4]
        ORRS     R0,R0,R1
        LDRH     R1,[R5, #+8]
        ORRS     R1,R1,R0
        LDRH     R0,[R5, #+10]
        ORRS     R0,R0,R1
//  187 
//  188 /*---------------------------- USART CR3 Configuration -----------------------*/  
//  189   tmpreg = USARTx->CR3;
//  190   /* Clear CTSE and RTSE bits */
//  191   tmpreg &= CR3_CLEAR_Mask;
//  192 
//  193   /* Configure the USART HFC -------------------------------------------------*/
//  194   /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
//  195   tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
//  196 
//  197   /* Write to USART CR3 */
//  198   USARTx->CR3 = (u16)tmpreg;
        LDR.N    R1,??USART_Init_0+0x8  ;; 0xfcff
        STRH     R0,[R4, #+12]
        LDRH     R0,[R4, #+20]
        ANDS     R1,R1,R0
        LDRH     R0,[R5, #+12]
        ORRS     R0,R0,R1
        STRH     R0,[R4, #+20]
//  199 
//  200 /*---------------------------- USART BRR Configuration -----------------------*/
//  201   /* Configure the USART Baud Rate -------------------------------------------*/
//  202   RCC_GetClocksFreq(&RCC_ClocksStatus);
        MOV      R0,SP
        _BLF     RCC_GetClocksFreq,??RCC_GetClocksFreq??rT
//  203   if (usartxbase == USART1_BASE)
        LDR.N    R0,??DataTable1  ;; 0x40013800
        CMP      R4,R0
        ITE     NE 
        LDRNE    R0,[SP, #+8]
//  204   {
//  205     apbclock = RCC_ClocksStatus.PCLK2_Frequency;
        LDREQ    R0,[SP, #+12]
//  206   }
//  207   else
//  208   {
//  209     apbclock = RCC_ClocksStatus.PCLK1_Frequency;
//  210   }
//  211 
//  212   /* Determine the integer part */
//  213   integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
        MOVS     R1,#+25
//  214   tmpreg = (integerdivider / 0x64) << 0x04;
//  215 
//  216   /* Determine the fractional part */
//  217   fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
//  218   tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
//  219 
//  220   /* Write to USART BRR */
//  221   USARTx->BRR = (u16)tmpreg;
        MOVS     R3,#+100
        MULS     R0,R1,R0
        LDR      R1,[R5, #+0]
        LSLS     R1,R1,#+2
        UDIV     R1,R0,R1
        MOVS     R0,#+100
        UDIV     R0,R1,R0
        LSLS     R2,R0,#+4
        MOVS     R0,R2
        LSRS     R2,R2,#+4
        MLS      R1,R2,R3,R1
        LSLS     R1,R1,#+4
        ADDS     R1,R1,#+50
        UDIV     R1,R1,R3
        LSLS     R1,R1,#+28
        LSRS     R1,R1,#+28
        ORRS     R1,R1,R0
        STRH     R1,[R4, #+8]
//  222 }
        ADD      SP,SP,#+20
        CFI CFA R13+12
        POP      {R4,R5,PC}       ;; return
        Nop      
        DATA
??USART_Init_0:
        DC32     0xcfff
        DC32     0xe9f3
        DC32     0xfcff
        CFI EndBlock cfiBlock1

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable1:
        DC32     0x40013800
//  223 
//  224 /*******************************************************************************
//  225 * Function Name  : USART_StructInit
//  226 * Description    : Fills each USART_InitStruct member with its default value.
//  227 * Input          : - USART_InitStruct: pointer to a USART_InitTypeDef structure
//  228 *                    which will be initialized.
//  229 * Output         : None
//  230 * Return         : None
//  231 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock2 Using cfiCommon0
        CFI Function USART_StructInit
        THUMB
//  232 void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
//  233 {
//  234   /* USART_InitStruct members default value */
//  235   USART_InitStruct->USART_BaudRate = 9600;
USART_StructInit:
        MOVS     R1,#+9600
        STR      R1,[R0, #+0]
//  236   USART_InitStruct->USART_WordLength = USART_WordLength_8b;
        MOVS     R1,#+0
        STRH     R1,[R0, #+4]
//  237   USART_InitStruct->USART_StopBits = USART_StopBits_1;
        STRH     R1,[R0, #+6]
//  238   USART_InitStruct->USART_Parity = USART_Parity_No ;
        STRH     R1,[R0, #+8]
//  239   USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
        MOVS     R2,#+12
        STRH     R2,[R0, #+10]
//  240   USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
        STRH     R1,[R0, #+12]
//  241 }
        BX       LR               ;; return
        CFI EndBlock cfiBlock2
//  242 
//  243 /*******************************************************************************
//  244 * Function Name  : USART_ClockInit
//  245 * Description    : Initializes the USARTx peripheral Clock according to the 
//  246 *                  specified parameters in the USART_ClockInitStruct .
//  247 * Input          : - USARTx: where x can be 1, 2, 3 to select the USART peripheral.
//  248 *                    Note: The Smart Card mode is not available for UART4 and UART5.
//  249 *                  - USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
//  250 *                    structure that contains the configuration information for 
//  251 *                    the specified USART peripheral.
//  252 * Output         : None
//  253 * Return         : None
//  254 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock3 Using cfiCommon0
        CFI Function USART_ClockInit
        THUMB
//  255 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
//  256 {
//  257   u32 tmpreg = 0x00;
//  258 
//  259   /* Check the parameters */
//  260   assert_param(IS_USART_123_PERIPH(USARTx));
//  261   assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
//  262   assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
//  263   assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
//  264   assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));              
//  265   
//  266 /*---------------------------- USART CR2 Configuration -----------------------*/
//  267   tmpreg = USARTx->CR2;
USART_ClockInit:
        LDRH     R2,[R0, #+16]
//  268   /* Clear CLKEN, CPOL, CPHA and LBCL bits */
//  269   tmpreg &= CR2_CLOCK_CLEAR_Mask;
//  270 
//  271   /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
//  272   /* Set CLKEN bit according to USART_Clock value */
//  273   /* Set CPOL bit according to USART_CPOL value */
//  274   /* Set CPHA bit according to USART_CPHA value */
//  275   /* Set LBCL bit according to USART_LastBit value */
//  276   tmpreg |= (u32)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
//  277                  USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
//  278 
//  279   /* Write to USART CR2 */
//  280   USARTx->CR2 = (u16)tmpreg;
        LDR.N    R3,??USART_ClockInit_0  ;; 0xf0ff
        ANDS     R3,R3,R2
        LDRH     R2,[R1, #+0]
        ORRS     R2,R2,R3
        LDRH     R3,[R1, #+2]