📄 stm32f10x_tim.s79
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TIM_ICInit:
PUSH {R4-R7,LR}
CFI ?RET Frame(CFA, -4)
CFI R7 Frame(CFA, -8)
CFI R6 Frame(CFA, -12)
CFI R5 Frame(CFA, -16)
CFI R4 Frame(CFA, -20)
CFI CFA R13+20
MOVS R5,R1
// 587 /* Check the parameters */
// 588 assert_param(IS_TIM_123458_PERIPH(TIMx));
// 589 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
// 590 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
// 591 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
// 592 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
// 593 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
// 594
// 595 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
LDRH R1,[R5, #+2]
LDRH R2,[R5, #+4]
LDRH R3,[R5, #+8]
MOVS R4,R0
LDRH R0,[R5, #+0]
CBNZ R0,??TIM_ICInit_0
// 596 {
// 597 /* TI1 Configuration */
// 598 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
// 599 TIM_ICInitStruct->TIM_ICSelection,
// 600 TIM_ICInitStruct->TIM_ICFilter);
B.N ?Subroutine2
// 601
// 602 /* Set the Input Capture Prescaler value */
// 603 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
// 604 }
// 605 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
??TIM_ICInit_0:
CMP R0,#+4
BNE.N ??TIM_ICInit_1
// 606 {
// 607 /* TI2 Configuration */
// 608 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
// 609 TIM_ICInitStruct->TIM_ICSelection,
// 610 TIM_ICInitStruct->TIM_ICFilter);
B.N ?Subroutine1
// 611
// 612 /* Set the Input Capture Prescaler value */
// 613 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
// 614 }
// 615 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
??TIM_ICInit_1:
CMP R0,#+8
LDRH R0,[R4, #+32]
BNE.N ??TIM_ICInit_2
// 616 {
// 617 /* TI3 Configuration */
// 618 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
// 619 TIM_ICInitStruct->TIM_ICSelection,
// 620 TIM_ICInitStruct->TIM_ICFilter);
LDR.N R6,??DataTable29 ;; 0xfeff
LDR.N R7,??DataTable30 ;; 0xff0c
ANDS R6,R6,R0
STRH R6,[R4, #+32]
LDRH R6,[R4, #+28]
LDRH R0,[R4, #+32]
ANDS R7,R7,R6
ORRS R2,R2,R7
ORRS R2,R2,R3, LSL #+4
STRH R2,[R4, #+28]
LDR.N R2,??DataTable31 ;; 0xfdff
ANDS R2,R2,R0
ORRS R0,R2,R1, LSL #+8
ORRS R0,R0,#0x100
STRH R0,[R4, #+32]
// 621
// 622 /* Set the Input Capture Prescaler value */
// 623 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
LDRH R1,[R5, #+6]
MOVS R0,R4
BL TIM_SetIC3Prescaler
POP {R4-R7,PC}
// 624 }
// 625 else
// 626 {
// 627 /* TI4 Configuration */
// 628 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
// 629 TIM_ICInitStruct->TIM_ICSelection,
// 630 TIM_ICInitStruct->TIM_ICFilter);
??TIM_ICInit_2:
LDR.N R6,??DataTable32 ;; 0xefff
LDR.N R7,??DataTable33 ;; 0xcff
ANDS R6,R6,R0
STRH R6,[R4, #+32]
LDRH R6,[R4, #+28]
LDRH R0,[R4, #+32]
ANDS R7,R7,R6
ORRS R2,R7,R2, LSL #+8
ORRS R2,R2,R3, LSL #+12
STRH R2,[R4, #+28]
LDR.N R2,??DataTable34 ;; 0xdfff
ANDS R2,R2,R0
ORRS R0,R2,R1, LSL #+12
ORRS R0,R0,#0x1000
STRH R0,[R4, #+32]
// 631
// 632 /* Set the Input Capture Prescaler value */
// 633 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
LDRH R1,[R5, #+6]
MOVS R0,R4
BL TIM_SetIC4Prescaler
// 634 }
// 635 }
POP {R4-R7,PC} ;; return
CFI EndBlock cfiBlock6
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable29:
DC32 0xfeff
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable30:
DC32 0xff0c
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable31:
DC32 0xfdff
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable32:
DC32 0xefff
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable33:
DC32 0xcff
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable34:
DC32 0xdfff
// 636
// 637 /*******************************************************************************
// 638 * Function Name : TIM_PWMIConfig
// 639 * Description : Configures the TIM peripheral according to the specified
// 640 * parameters in the TIM_ICInitStruct to measure an external PWM
// 641 * signal.
// 642 * Input : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM
// 643 * peripheral.
// 644 * - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
// 645 * that contains the configuration information for the specified
// 646 * TIM peripheral.
// 647 * Output : None
// 648 * Return : None
// 649 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock7 Using cfiCommon0
CFI Function TIM_PWMIConfig
THUMB
// 650 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
// 651 {
TIM_PWMIConfig:
PUSH {R4-R7,LR}
CFI ?RET Frame(CFA, -4)
CFI R7 Frame(CFA, -8)
CFI R6 Frame(CFA, -12)
CFI R5 Frame(CFA, -16)
CFI R4 Frame(CFA, -20)
CFI CFA R13+20
MOVS R5,R1
// 652 u16 icoppositepolarity = TIM_ICPolarity_Rising;
// 653 u16 icoppositeselection = TIM_ICSelection_DirectTI;
// 654
// 655 /* Check the parameters */
// 656 assert_param(IS_TIM_123458_PERIPH(TIMx));
// 657
// 658 /* Select the Opposite Input Polarity */
// 659 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
LDRH R1,[R5, #+2]
MOVS R4,R0
MOVS R7,#+2
CMP R1,#+0
ITE NE
MOVNE R6,#+0
// 660 {
// 661 icoppositepolarity = TIM_ICPolarity_Falling;
MOVEQ R6,#+2
// 662 }
// 663 else
// 664 {
// 665 icoppositepolarity = TIM_ICPolarity_Rising;
// 666 }
// 667
// 668 /* Select the Opposite Input */
// 669 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
LDRH R2,[R5, #+4]
CMP R2,#+1
IT NE
// 670 {
// 671 icoppositeselection = TIM_ICSelection_IndirectTI;
// 672 }
// 673 else
// 674 {
// 675 icoppositeselection = TIM_ICSelection_DirectTI;
MOVNE R7,#+1
// 676 }
// 677
// 678 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
LDRH R3,[R5, #+8]
LDRH R0,[R5, #+0]
CBNZ R0,??TIM_PWMIConfig_0
// 679 {
// 680 /* TI1 Configuration */
// 681 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
// 682 TIM_ICInitStruct->TIM_ICFilter);
MOVS R0,R4
BL TI1_Config
// 683
// 684 /* Set the Input Capture Prescaler value */
// 685 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
LDRH R1,[R5, #+6]
MOVS R0,R4
BL TIM_SetIC1Prescaler
// 686
// 687 /* TI2 Configuration */
// 688 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
LDRH R3,[R5, #+8]
MOVS R2,R7
MOVS R1,R6
B.N ?Subroutine1
// 689
// 690 /* Set the Input Capture Prescaler value */
// 691 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
// 692 }
// 693 else
// 694 {
// 695 /* TI2 Configuration */
// 696 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
// 697 TIM_ICInitStruct->TIM_ICFilter);
??TIM_PWMIConfig_0:
MOVS R0,R4
BL TI2_Config
// 698
// 699 /* Set the Input Capture Prescaler value */
// 700 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
LDRH R1,[R5, #+6]
MOVS R0,R4
BL TIM_SetIC2Prescaler
// 701
// 702 /* TI1 Configuration */
// 703 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
LDRH R3,[R5, #+8]
MOVS R2,R7
MOVS R1,R6
Nop
CFI EndBlock cfiBlock7
REQUIRE ?Subroutine2
;; // Fall through to label ?Subroutine2
// 704
// 705 /* Set the Input Capture Prescaler value */
// 706 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
// 707 }
// 708 }
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock8 Using cfiCommon0
CFI NoFunction
CFI CFA R13+20
CFI R4 Frame(CFA, -20)
CFI R5 Frame(CFA, -16)
CFI R6 Frame(CFA, -12)
CFI R7 Frame(CFA, -8)
CFI ?RET Frame(CFA, -4)
THUMB
?Subroutine2:
MOVS R0,R4
BL TI1_Config
LDRH R1,[R5, #+6]
MOVS R0,R4
BL TIM_SetIC1Prescaler
POP {R4-R7,PC}
CFI EndBlock cfiBlock8
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock9 Using cfiCommon0
CFI NoFunction
CFI CFA R13+20
CFI R4 Frame(CFA, -20)
CFI R5 Frame(CFA, -16)
CFI R6 Frame(CFA, -12)
CFI R7 Frame(CFA, -8)
CFI ?RET Frame(CFA, -4)
THUMB
?Subroutine1:
MOVS R0,R4
BL TI2_Config
LDRH R1,[R5, #+6]
MOVS R0,R4
BL TIM_SetIC2Prescaler
POP {R4-R7,PC}
CFI EndBlock cfiBlock9
// 709
// 710 /*******************************************************************************
// 711 * Function Name : TIM_BDTRConfig
// 712 * Description : Configures the: Break feature, dead time, Lock level, the OSSI,
// 713 * the OSSR State and the AOE(automatic output enable).
// 714 * Input :- TIMx: where x can be 1 or 8 to select the TIM
// 715 * - TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef
// 716 * structure that contains the BDTR Register configuration
// 717 * information for the TIM peripheral.
// 718 * Output : None
// 719 * Return : None
// 720 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock10 Using cfiCommon0
CFI Function TIM_BDTRConfig
THUMB
// 721 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
// 722 {
// 723 /* Check the parameters */
// 724 assert_param(IS_TIM_18_PERIPH(TIMx));
// 725 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
// 726 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
// 727 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
// 728 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
// 729 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
// 730 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
// 731
// 732 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
// 733 the OSSI State, the dead time value and the Automatic Output Enable Bit */
// 734
// 735 TIMx->BDTR = (u32)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
// 736 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
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