stm32f10x_tim.s79

用于监视I2C通信总线

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable11:
        DC32     0xffef

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        DATA
??DataTable13:
        DC32     0xffdf

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        DATA
??DataTable16:
        DC32     0xff7f
//  407 
//  408 /*******************************************************************************
//  409 * Function Name  : TIM_OC3Init
//  410 * Description    : Initializes the TIMx Channel3 according to the specified
//  411 *                  parameters in the TIM_OCInitStruct.
//  412 * Input          : - TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM 
//  413 *                    peripheral.
//  414 *                  - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
//  415 *                    that contains the configuration information for the specified
//  416 *                    TIM peripheral.
//  417 * Output         : None
//  418 * Return         : None
//  419 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock4 Using cfiCommon0
        CFI Function TIM_OC3Init
        THUMB
//  420 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
//  421 {
//  422   u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
//  423    
//  424   /* Check the parameters */
//  425   assert_param(IS_TIM_123458_PERIPH(TIMx)); 
//  426   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
//  427   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
//  428   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
//  429 
//  430   /* Disable the Channel 2: Reset the CC2E Bit */
//  431   TIMx->CCER &= CCER_CC3E_Reset;
TIM_OC3Init:
        LDR.N    R3,??DataTable29  ;; 0xfeff
        PUSH     {R4-R6,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R6 Frame(CFA, -8)
        CFI R5 Frame(CFA, -12)
        CFI R4 Frame(CFA, -16)
        CFI CFA R13+16
        LDRH     R2,[R0, #+32]
//  432   
//  433   /* Get the TIMx CCER register value */
//  434   tmpccer = TIMx->CCER;
//  435 
//  436   /* Get the TIMx CR2 register value */
//  437   tmpcr2 =  TIMx->CR2;
//  438   
//  439   /* Get the TIMx CCMR2 register value */
//  440   tmpccmrx = TIMx->CCMR2;
//  441     
//  442   /* Reset the Output Compare Mode Bits */
//  443   tmpccmrx &= CCMR_OC13M_Mask;
//  444   
//  445   /* Select the Output Compare Mode */
//  446   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
        LDR.N    R5,??DataTable18  ;; 0xff8f
        ANDS     R3,R3,R2
        STRH     R3,[R0, #+32]
        LDRH     R4,[R0, #+32]
        LDRH     R2,[R0, #+4]
        LDRH     R3,[R0, #+28]
//  447   
//  448   /* Reset the Output Polarity level */
//  449   tmpccer &= CCER_CC3P_Reset;
//  450 
//  451   /* Set the Output Compare Polarity */
//  452   tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 8);
//  453   
//  454   /* Set the Output State */
//  455   tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 8);
        LDRH     R6,[R1, #+2]
        ANDS     R5,R5,R3
        LDRH     R3,[R1, #+0]
        ORRS     R3,R3,R5
        LDR.N    R5,??DataTable31  ;; 0xfdff
        ANDS     R5,R5,R4
        LDRH     R4,[R1, #+8]
        ORRS     R6,R6,R4
        ORRS     R4,R5,R6, LSL #+8
//  456   
//  457   /* Set the Capture Compare Register value */
//  458   TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
        LDRH     R5,[R1, #+6]
        STRH     R5,[R0, #+60]
//  459   
//  460   if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
        LDR.N    R5,??DataTable27  ;; 0x40012c00
        CMP      R0,R5
        BEQ.N    ??TIM_OC3Init_0
        LDR.N    R5,??DataTable28  ;; 0x40013400
        CMP      R0,R5
        BNE.N    ??TIM_OC3Init_1
//  461   {
//  462     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
//  463     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
//  464     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
//  465     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
//  466     
//  467     /* Reset the Output N Polarity level */
//  468     tmpccer &= CCER_CC3NP_Reset;
//  469 
//  470     /* Set the Output N Polarity */
//  471     tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
//  472 
//  473     /* Reset the Output N State */
//  474     tmpccer &= CCER_CC3NE_Reset;
//  475     
//  476     /* Set the Output N State */
//  477     tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 8);
??TIM_OC3Init_0:
        LDR.N    R5,??DataTable22  ;; 0xf7ff
        ANDS     R5,R5,R4
        LDRH     R4,[R1, #+10]
        ORRS     R4,R5,R4, LSL #+8
        LDR.N    R5,??DataTable23  ;; 0xfbff
        ANDS     R5,R5,R4
        LDRH     R4,[R1, #+4]
        ORRS     R4,R5,R4, LSL #+8
//  478 
//  479     /* Reset the Ouput Compare and Output Compare N IDLE State */
//  480     tmpcr2 &= CR2_OIS3_Reset;
//  481     tmpcr2 &= CR2_OIS3N_Reset;
//  482 
//  483     /* Set the Output Idle state */
//  484     tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 4);
//  485 
//  486     /* Set the Output N Idle state */
//  487     tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
        LDR.N    R5,??TIM_OC3Init_2  ;; 0x4fff
        ANDS     R5,R5,R2
        LDRH     R2,[R1, #+12]
        LDRH     R1,[R1, #+14]
        ORRS     R1,R1,R2
        ORRS     R2,R5,R1, LSL #+4
//  488   }
//  489 
//  490   /* Write to TIMx CR2 */
//  491   TIMx->CR2 = tmpcr2;
??TIM_OC3Init_1:
        STRH     R2,[R0, #+4]
//  492   
//  493   /* Write to TIMx CCMR2 */
//  494   TIMx->CCMR2 = tmpccmrx;
        STRH     R3,[R0, #+28]
//  495   
//  496   /* Write to TIMx CCER */
//  497   TIMx->CCER = tmpccer;
        STRH     R4,[R0, #+32]
//  498 }
        POP      {R4-R6,PC}       ;; return
        DATA
??TIM_OC3Init_2:
        DC32     0x4fff
        CFI EndBlock cfiBlock4

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable18:
        DC32     0xff8f

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable22:
        DC32     0xf7ff

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable23:
        DC32     0xfbff
//  499 
//  500 /*******************************************************************************
//  501 * Function Name  : TIM_OC4Init
//  502 * Description    : Initializes the TIMx Channel4 according to the specified
//  503 *                  parameters in the TIM_OCInitStruct.
//  504 * Input          : - TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM 
//  505 *                    peripheral.
//  506 *                  - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
//  507 *                    that contains the configuration information for the specified
//  508 *                    TIM peripheral.
//  509 * Output         : None
//  510 * Return         : None
//  511 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock5 Using cfiCommon0
        CFI Function TIM_OC4Init
        THUMB
//  512 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
//  513 {
//  514   u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
//  515    
//  516   /* Check the parameters */
//  517   assert_param(IS_TIM_123458_PERIPH(TIMx)); 
//  518   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
//  519   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
//  520   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
//  521 
//  522   /* Disable the Channel 2: Reset the CC4E Bit */
//  523   TIMx->CCER &= CCER_CC4E_Reset;
TIM_OC4Init:
        LDR.N    R3,??DataTable32  ;; 0xefff
        PUSH     {R4-R6,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R6 Frame(CFA, -8)
        CFI R5 Frame(CFA, -12)
        CFI R4 Frame(CFA, -16)
        CFI CFA R13+16
        LDRH     R2,[R0, #+32]
//  524   
//  525   /* Get the TIMx CCER register value */
//  526   tmpccer = TIMx->CCER;
//  527 
//  528   /* Get the TIMx CR2 register value */
//  529   tmpcr2 =  TIMx->CR2;
//  530   
//  531   /* Get the TIMx CCMR2 register value */
//  532   tmpccmrx = TIMx->CCMR2;
//  533     
//  534   /* Reset the Output Compare Mode Bits */
//  535   tmpccmrx &= CCMR_OC24M_Mask;
//  536   
//  537   /* Select the Output Compare Mode */
//  538   tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
        LDR.N    R5,??DataTable25  ;; 0x8fff
        ANDS     R3,R3,R2
        STRH     R3,[R0, #+32]
        LDRH     R3,[R0, #+32]
        LDRH     R2,[R0, #+4]
        LDRH     R4,[R0, #+28]
//  539   
//  540   /* Reset the Output Polarity level */
//  541   tmpccer &= CCER_CC4P_Reset;
//  542 
//  543   /* Set the Output Compare Polarity */
//  544   tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 12);
//  545   
//  546   /* Set the Output State */
//  547   tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 12);
        LDRH     R6,[R1, #+2]
        ANDS     R5,R5,R4
        LDRH     R4,[R1, #+0]
        ORRS     R4,R5,R4, LSL #+8
        LDR.N    R5,??DataTable34  ;; 0xdfff
        ANDS     R5,R5,R3
        LDRH     R3,[R1, #+8]
        ORRS     R6,R6,R3
        ORRS     R3,R5,R6, LSL #+12
//  548   
//  549   /* Set the Capture Compare Register value */
//  550   TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
        LDRH     R5,[R1, #+6]
        STRH     R5,[R0, #+64]
//  551   
//  552   if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
        LDR.N    R5,??DataTable27  ;; 0x40012c00
        CMP      R0,R5
        BEQ.N    ??TIM_OC4Init_0
        LDR.N    R5,??DataTable28  ;; 0x40013400
        CMP      R0,R5
        BNE.N    ??TIM_OC4Init_1
//  553   {
//  554     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
//  555 
//  556     /* Reset the Ouput Compare IDLE State */
//  557     tmpcr2 &= CR2_OIS4_Reset;
//  558 
//  559     /* Set the Output Idle state */
//  560     tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 6);
??TIM_OC4Init_0:
        LDRH     R1,[R1, #+12]
        LSLS     R2,R2,#+18
        LSRS     R2,R2,#+18
        ORRS     R2,R2,R1, LSL #+6
//  561   }
//  562 
//  563   /* Write to TIMx CR2 */
//  564   TIMx->CR2 = tmpcr2;
??TIM_OC4Init_1:
        STRH     R2,[R0, #+4]
//  565   
//  566   /* Write to TIMx CCMR2 */  
//  567   TIMx->CCMR2 = tmpccmrx;
        STRH     R4,[R0, #+28]
//  568   
//  569   /* Write to TIMx CCER */
//  570   TIMx->CCER = tmpccer;
        STRH     R3,[R0, #+32]
//  571 }
        POP      {R4-R6,PC}       ;; return
        CFI EndBlock cfiBlock5

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable25:
        DC32     0x8fff

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable27:
        DC32     0x40012c00

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        DATA
??DataTable28:
        DC32     0x40013400
//  572 
//  573 /*******************************************************************************
//  574 * Function Name  : TIM_ICInit
//  575 * Description    : Initializes the TIM peripheral according to the specified
//  576 *                  parameters in the TIM_ICInitStruct.
//  577 * Input          : - TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM 
//  578 *                    peripheral.
//  579 *                  - TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
//  580 *                    that contains the configuration information for the specified
//  581 *                    TIM peripheral.
//  582 * Output         : None
//  583 * Return         : None
//  584 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock6 Using cfiCommon0
        CFI Function TIM_ICInit
        THUMB
//  585 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
//  586 {