stm32f10x_tim.s79

用于监视I2C通信总线

//  220     /* Set the Repetition Counter value */
//  221     TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
??TIM_TimeBaseInit_0:
        LDRB     R1,[R1, #+8]
        STRH     R1,[R0, #+48]
//  222   }        
//  223 }
??TIM_TimeBaseInit_1:
        POP      {R4,PC}          ;; return
        CFI EndBlock cfiBlock1
//  224 
//  225 /*******************************************************************************
//  226 * Function Name  : TIM_OC1Init
//  227 * Description    : Initializes the TIMx Channel1 according to the specified
//  228 *                  parameters in the TIM_OCInitStruct.
//  229 * Input          : - TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM 
//  230 *                    peripheral.
//  231 *                  - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
//  232 *                    that contains the configuration information for the specified
//  233 *                    TIM peripheral.
//  234 * Output         : None
//  235 * Return         : None
//  236 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock2 Using cfiCommon0
        CFI Function TIM_OC1Init
        THUMB
//  237 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
//  238 {
//  239   u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
//  240    
//  241   /* Check the parameters */
//  242   assert_param(IS_TIM_123458_PERIPH(TIMx)); 
//  243   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
//  244   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
//  245   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
//  246 
//  247   /* Disable the Channel 1: Reset the CC1E Bit */
//  248   TIMx->CCER &= CCER_CC1E_Reset;
TIM_OC1Init:
        LDR.N    R3,??DataTable4  ;; 0xfffe
        PUSH     {R4-R6,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R6 Frame(CFA, -8)
        CFI R5 Frame(CFA, -12)
        CFI R4 Frame(CFA, -16)
        CFI CFA R13+16
        LDRH     R2,[R0, #+32]
//  249   
//  250   /* Get the TIMx CCER register value */
//  251   tmpccer = TIMx->CCER;
//  252 
//  253   /* Get the TIMx CR2 register value */
//  254   tmpcr2 =  TIMx->CR2;
//  255   
//  256   /* Get the TIMx CCMR1 register value */
//  257   tmpccmrx = TIMx->CCMR1;
//  258     
//  259   /* Reset the Output Compare Mode Bits */
//  260   tmpccmrx &= CCMR_OC13M_Mask;
//  261   
//  262   /* Select the Output Compare Mode */
//  263   tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
        LDR.N    R5,??DataTable18  ;; 0xff8f
        ANDS     R3,R3,R2
        STRH     R3,[R0, #+32]
        LDRH     R4,[R0, #+32]
        LDRH     R2,[R0, #+4]
        LDRH     R3,[R0, #+24]
//  264   
//  265   /* Reset the Output Polarity level */
//  266   tmpccer &= CCER_CC1P_Reset;
//  267 
//  268   /* Set the Output Compare Polarity */
//  269   tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
//  270   
//  271   /* Set the Output State */
//  272   tmpccer |= TIM_OCInitStruct->TIM_OutputState;
        LDRH     R6,[R1, #+8]
        ANDS     R5,R5,R3
        LDRH     R3,[R1, #+0]
        ORRS     R3,R3,R5
        LDR.N    R5,??DataTable6  ;; 0xfffd
        ANDS     R5,R5,R4
        LDRH     R4,[R1, #+2]
        ORRS     R6,R6,R5
//  273   
//  274   /* Set the Capture Compare Register value */
//  275   TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
        LDRH     R5,[R1, #+6]
        ORRS     R4,R4,R6
        STRH     R5,[R0, #+52]
//  276   
//  277   if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
        LDR.N    R5,??DataTable27  ;; 0x40012c00
        CMP      R0,R5
        BEQ.N    ??TIM_OC1Init_0
        LDR.N    R5,??DataTable28  ;; 0x40013400
        CMP      R0,R5
        BNE.N    ??TIM_OC1Init_1
//  278   {
//  279     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
//  280     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
//  281     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
//  282     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
//  283     
//  284     /* Reset the Output N Polarity level */
//  285     tmpccer &= CCER_CC1NP_Reset;
//  286 
//  287     /* Set the Output N Polarity */
//  288     tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
//  289 
//  290     /* Reset the Output N State */
//  291     tmpccer &= CCER_CC1NE_Reset;
//  292     
//  293     /* Set the Output N State */
//  294     tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
??TIM_OC1Init_0:
        LDR.N    R5,??DataTable9  ;; 0xfff7
//  295 
//  296     /* Reset the Ouput Compare and Output Compare N IDLE State */
//  297     tmpcr2 &= CR2_OIS1_Reset;
//  298     tmpcr2 &= CR2_OIS1N_Reset;
//  299 
//  300     /* Set the Output Idle state */
//  301     tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
//  302 
//  303     /* Set the Output N Idle state */
//  304     tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
        LDRH     R6,[R1, #+12]
        ANDS     R5,R5,R4
        LDRH     R4,[R1, #+10]
        ORRS     R4,R4,R5
        LDR.N    R5,??DataTable10  ;; 0xfffb
        ANDS     R5,R5,R4
        LDRH     R4,[R1, #+4]
        ORRS     R4,R4,R5
        LDR.N    R5,??TIM_OC1Init_2  ;; 0x7cff
        ANDS     R5,R5,R2
        LDRH     R2,[R1, #+14]
        ORRS     R6,R6,R5
        ORRS     R2,R2,R6
//  305   }
//  306   /* Write to TIMx CR2 */
//  307   TIMx->CR2 = tmpcr2;
??TIM_OC1Init_1:
        STRH     R2,[R0, #+4]
//  308   
//  309   /* Write to TIMx CCMR1 */
//  310   TIMx->CCMR1 = tmpccmrx;
        STRH     R3,[R0, #+24]
//  311   
//  312   /* Write to TIMx CCER */
//  313   TIMx->CCER = tmpccer;
        STRH     R4,[R0, #+32]
//  314 }
        POP      {R4-R6,PC}       ;; return
        DATA
??TIM_OC1Init_2:
        DC32     0x7cff
        CFI EndBlock cfiBlock2

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable4:
        DC32     0xfffe

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable6:
        DC32     0xfffd

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable9:
        DC32     0xfff7

        RSEG CODE:CODE:NOROOT(2)
        DATA
??DataTable10:
        DC32     0xfffb
//  315 
//  316 /*******************************************************************************
//  317 * Function Name  : TIM_OC2Init
//  318 * Description    : Initializes the TIMx Channel2 according to the specified
//  319 *                  parameters in the TIM_OCInitStruct.
//  320 * Input          : - TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM 
//  321 *                    peripheral.
//  322 *                  - TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
//  323 *                    that contains the configuration information for the specified
//  324 *                    TIM peripheral.
//  325 * Output         : None
//  326 * Return         : None
//  327 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock3 Using cfiCommon0
        CFI Function TIM_OC2Init
        THUMB
//  328 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
//  329 {
//  330   u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
//  331    
//  332   /* Check the parameters */
//  333   assert_param(IS_TIM_123458_PERIPH(TIMx)); 
//  334   assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
//  335   assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
//  336   assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
//  337 
//  338   /* Disable the Channel 2: Reset the CC2E Bit */
//  339   TIMx->CCER &= CCER_CC2E_Reset;
TIM_OC2Init:
        LDR.N    R3,??DataTable11  ;; 0xffef
        PUSH     {R4-R6,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R6 Frame(CFA, -8)
        CFI R5 Frame(CFA, -12)
        CFI R4 Frame(CFA, -16)
        CFI CFA R13+16
        LDRH     R2,[R0, #+32]
//  340   
//  341   /* Get the TIMx CCER register value */  
//  342   tmpccer = TIMx->CCER;
//  343 
//  344   /* Get the TIMx CR2 register value */
//  345   tmpcr2 =  TIMx->CR2;
//  346   
//  347   /* Get the TIMx CCMR1 register value */
//  348   tmpccmrx = TIMx->CCMR1;
//  349     
//  350   /* Reset the Output Compare Mode Bits */
//  351   tmpccmrx &= CCMR_OC24M_Mask;
//  352   
//  353   /* Select the Output Compare Mode */
//  354   tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
        LDR.N    R5,??DataTable25  ;; 0x8fff
        ANDS     R3,R3,R2
        STRH     R3,[R0, #+32]
        LDRH     R3,[R0, #+32]
        LDRH     R2,[R0, #+4]
        LDRH     R4,[R0, #+24]
//  355   
//  356   /* Reset the Output Polarity level */
//  357   tmpccer &= CCER_CC2P_Reset;
//  358 
//  359   /* Set the Output Compare Polarity */
//  360   tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 4);
//  361   
//  362   /* Set the Output State */
//  363   tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 4);
        LDRH     R6,[R1, #+2]
        ANDS     R5,R5,R4
        LDRH     R4,[R1, #+0]
        ORRS     R4,R5,R4, LSL #+8
        LDR.N    R5,??DataTable13  ;; 0xffdf
        ANDS     R5,R5,R3
        LDRH     R3,[R1, #+8]
        ORRS     R6,R6,R3
        ORRS     R3,R5,R6, LSL #+4
//  364   
//  365   /* Set the Capture Compare Register value */
//  366   TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
        LDRH     R5,[R1, #+6]
        STRH     R5,[R0, #+56]
//  367   
//  368   if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
        LDR.N    R5,??DataTable27  ;; 0x40012c00
        CMP      R0,R5
        BEQ.N    ??TIM_OC2Init_0
        LDR.N    R5,??DataTable28  ;; 0x40013400
        CMP      R0,R5
        BNE.N    ??TIM_OC2Init_1
//  369   {
//  370     assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
//  371     assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
//  372     assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
//  373     assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
//  374     
//  375     /* Reset the Output N Polarity level */
//  376     tmpccer &= CCER_CC2NP_Reset;
//  377 
//  378     /* Set the Output N Polarity */
//  379     tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
//  380 
//  381     /* Reset the Output N State */
//  382     tmpccer &= CCER_CC2NE_Reset;
//  383     
//  384     /* Set the Output N State */
//  385     tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 4);
??TIM_OC2Init_0:
        LDR.N    R5,??DataTable16  ;; 0xff7f
        ANDS     R5,R5,R3
        LDRH     R3,[R1, #+10]
        ORRS     R3,R5,R3, LSL #+4
        LDR.N    R5,??TIM_OC2Init_2  ;; 0xffbf
        ANDS     R5,R5,R3
        LDRH     R3,[R1, #+4]
        ORRS     R3,R5,R3, LSL #+4
//  386 
//  387     /* Reset the Ouput Compare and Output Compare N IDLE State */
//  388     tmpcr2 &= CR2_OIS2_Reset;
//  389     tmpcr2 &= CR2_OIS2N_Reset;
//  390 
//  391     /* Set the Output Idle state */
//  392     tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 2);
//  393 
//  394     /* Set the Output N Idle state */
//  395     tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
        LDR.N    R5,??TIM_OC2Init_2+0x4  ;; 0x73ff
        ANDS     R5,R5,R2
        LDRH     R2,[R1, #+12]
        LDRH     R1,[R1, #+14]
        ORRS     R1,R1,R2
        ORRS     R2,R5,R1, LSL #+2
//  396   }
//  397 
//  398   /* Write to TIMx CR2 */
//  399   TIMx->CR2 = tmpcr2;
??TIM_OC2Init_1:
        STRH     R2,[R0, #+4]
//  400   
//  401   /* Write to TIMx CCMR1 */
//  402   TIMx->CCMR1 = tmpccmrx;
        STRH     R4,[R0, #+24]
//  403   
//  404   /* Write to TIMx CCER */
//  405   TIMx->CCER = tmpccer;
        STRH     R3,[R0, #+32]
//  406 }
        POP      {R4-R6,PC}       ;; return
        Nop      
        DATA
??TIM_OC2Init_2:
        DC32     0xffbf
        DC32     0x73ff
        CFI EndBlock cfiBlock3