stm32f10x_tim.s79

用于监视I2C通信总线

//   16 /* Includes ------------------------------------------------------------------*/
//   17 #include "stm32f10x_tim.h"
//   18 #include "stm32f10x_rcc.h"
//   19 
//   20 /* Private typedef -----------------------------------------------------------*/
//   21 /* Private define ------------------------------------------------------------*/
//   22 /* ---------------------- TIM registers bit mask ------------------------ */
//   23 #define CR1_CEN_Set                 ((u16)0x0001)
//   24 #define CR1_CEN_Reset               ((u16)0x03FE)
//   25 #define CR1_UDIS_Set                ((u16)0x0002)
//   26 #define CR1_UDIS_Reset              ((u16)0x03FD)
//   27 #define CR1_URS_Set                 ((u16)0x0004)
//   28 #define CR1_URS_Reset               ((u16)0x03FB)
//   29 #define CR1_OPM_Reset               ((u16)0x03F7)
//   30 #define CR1_CounterMode_Mask        ((u16)0x038F)
//   31 #define CR1_ARPE_Set                ((u16)0x0080)
//   32 #define CR1_ARPE_Reset              ((u16)0x037F)
//   33 #define CR1_CKD_Mask                ((u16)0x00FF)
//   34 
//   35 #define CR2_CCPC_Set                ((u16)0x0001)
//   36 #define CR2_CCPC_Reset              ((u16)0xFFFE)
//   37 #define CR2_CCUS_Set                ((u16)0x0004)
//   38 #define CR2_CCUS_Reset              ((u16)0xFFFB)
//   39 #define CR2_CCDS_Set                ((u16)0x0008)
//   40 #define CR2_CCDS_Reset              ((u16)0xFFF7)
//   41 #define CR2_MMS_Mask                ((u16)0xFF8F)
//   42 #define CR2_TI1S_Set                ((u16)0x0080)
//   43 #define CR2_TI1S_Reset              ((u16)0xFF7F)
//   44 #define CR2_OIS1_Reset              ((u16)0x7EFF)
//   45 #define CR2_OIS1N_Reset             ((u16)0x7DFF)
//   46 #define CR2_OIS2_Reset              ((u16)0x7BFF)
//   47 #define CR2_OIS2N_Reset             ((u16)0x77FF)
//   48 #define CR2_OIS3_Reset              ((u16)0x6FFF)
//   49 #define CR2_OIS3N_Reset             ((u16)0x5FFF)
//   50 #define CR2_OIS4_Reset              ((u16)0x3FFF)
//   51 
//   52 #define SMCR_SMS_Mask               ((u16)0xFFF8)
//   53 #define SMCR_ETR_Mask               ((u16)0x00FF)
//   54 #define SMCR_TS_Mask                ((u16)0xFF8F)
//   55 #define SMCR_MSM_Reset              ((u16)0xFF7F)
//   56 #define SMCR_ECE_Set                ((u16)0x4000)
//   57 
//   58 #define CCMR_CC13S_Mask             ((u16)0xFFFC)
//   59 #define CCMR_CC24S_Mask             ((u16)0xFCFF)
//   60 #define CCMR_TI13Direct_Set         ((u16)0x0001)
//   61 #define CCMR_TI24Direct_Set         ((u16)0x0100)
//   62 #define CCMR_OC13FE_Reset           ((u16)0xFFFB)
//   63 #define CCMR_OC24FE_Reset           ((u16)0xFBFF)
//   64 #define CCMR_OC13PE_Reset           ((u16)0xFFF7)
//   65 #define CCMR_OC24PE_Reset           ((u16)0xF7FF)
//   66 #define CCMR_OC13M_Mask             ((u16)0xFF8F)
//   67 #define CCMR_OC24M_Mask             ((u16)0x8FFF) 
//   68 
//   69 #define CCMR_OC13CE_Reset           ((u16)0xFF7F)
//   70 #define CCMR_OC24CE_Reset           ((u16)0x7FFF)
//   71 
//   72 #define CCMR_IC13PSC_Mask           ((u16)0xFFF3)
//   73 #define CCMR_IC24PSC_Mask           ((u16)0xF3FF)
//   74 #define CCMR_IC13F_Mask             ((u16)0xFF0F)
//   75 #define CCMR_IC24F_Mask             ((u16)0x0FFF)
//   76 
//   77 #define CCMR_Offset                 ((u16)0x0018)
//   78 #define CCER_CCE_Set                ((u16)0x0001)
//   79 #define	CCER_CCNE_Set               ((u16)0x0004)
//   80 
//   81 #define CCER_CC1P_Reset             ((u16)0xFFFD)
//   82 #define CCER_CC2P_Reset             ((u16)0xFFDF)
//   83 #define CCER_CC3P_Reset             ((u16)0xFDFF)
//   84 #define CCER_CC4P_Reset             ((u16)0xDFFF)
//   85 
//   86 #define CCER_CC1NP_Reset            ((u16)0xFFF7)
//   87 #define CCER_CC2NP_Reset            ((u16)0xFF7F)
//   88 #define CCER_CC3NP_Reset            ((u16)0xF7FF)
//   89 
//   90 #define CCER_CC1E_Set               ((u16)0x0001)
//   91 #define CCER_CC1E_Reset             ((u16)0xFFFE)
//   92 
//   93 #define CCER_CC1NE_Reset            ((u16)0xFFFB)
//   94 
//   95 #define CCER_CC2E_Set               ((u16)0x0010)
//   96 #define CCER_CC2E_Reset             ((u16)0xFFEF)
//   97 
//   98 #define CCER_CC2NE_Reset            ((u16)0xFFBF)
//   99 
//  100 #define CCER_CC3E_Set               ((u16)0x0100)
//  101 #define CCER_CC3E_Reset             ((u16)0xFEFF)
//  102 
//  103 #define CCER_CC3NE_Reset            ((u16)0xFBFF)
//  104 
//  105 #define CCER_CC4E_Set               ((u16)0x1000)
//  106 #define CCER_CC4E_Reset             ((u16)0xEFFF)
//  107 
//  108 #define BDTR_MOE_Set                ((u16)0x8000)
//  109 #define BDTR_MOE_Reset              ((u16)0x7FFF)
//  110 
//  111 /* Private macro -------------------------------------------------------------*/
//  112 /* Private variables ---------------------------------------------------------*/
//  113 /* Private function prototypes -----------------------------------------------*/
//  114 static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
//  115                        u16 TIM_ICFilter);
//  116 static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
//  117                        u16 TIM_ICFilter);
//  118 static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
//  119                        u16 TIM_ICFilter);
//  120 static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
//  121                        u16 TIM_ICFilter);
//  122 /* Private macro -------------------------------------------------------------*/
//  123 /* Private variables ---------------------------------------------------------*/
//  124 /* Private function prototypes -----------------------------------------------*/
//  125 /* Private functions ---------------------------------------------------------*/
//  126 /*******************************************************************************
//  127 * Function Name  : TIM_DeInit
//  128 * Description    : Deinitializes the TIMx peripheral registers to their default
//  129 *                  reset values.
//  130 * Input          : - TIMx: where x can be 1 to 8 to select the TIM peripheral.
//  131 * Output         : None
//  132 * Return         : None
//  133 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock0 Using cfiCommon0
        CFI Function TIM_DeInit
        THUMB
//  134 void TIM_DeInit(TIM_TypeDef* TIMx)
//  135 {
TIM_DeInit:
        PUSH     {LR}
        CFI ?RET Frame(CFA, -4)
        CFI CFA R13+4
//  136   /* Check the parameters */
//  137   assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
//  138  
//  139   switch (*(u32*)&TIMx)
        MOVS     R1,#[phone]
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_0
        LDR.N    R1,??TIM_DeInit_1  ;; 0x40000400
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_2
        LDR.N    R1,??TIM_DeInit_1+0x4  ;; 0x40000800
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_3
        LDR.N    R1,??TIM_DeInit_1+0x8  ;; 0x40000c00
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_4
        LDR.N    R1,??TIM_DeInit_1+0xC  ;; 0x40001000
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_5
        LDR.N    R1,??TIM_DeInit_1+0x10  ;; 0x40001400
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_6
        LDR.N    R1,??DataTable27  ;; 0x40012c00
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_7
        LDR.N    R1,??DataTable28  ;; 0x40013400
        CMP      R0,R1
        BEQ.N    ??TIM_DeInit_8
        POP      {PC}
//  140   {
//  141     case TIM1_BASE:
//  142       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
??TIM_DeInit_7:
        MOVS     R1,#+1
        LSLS     R0,R1,#+11
        _BLF     RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
//  143       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
        MOVS     R1,#+0
        MOVS     R0,#+2048
        B.N      ??TIM_DeInit_9
//  144       break; 
//  145       
//  146     case TIM2_BASE:
//  147       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
??TIM_DeInit_0:
        MOVS     R1,#+1
        MOVS     R0,#+1
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  148       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
        MOVS     R1,#+0
        MOVS     R0,#+1
        B.N      ??TIM_DeInit_10
//  149       break;
//  150  
//  151     case TIM3_BASE:
//  152       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
??TIM_DeInit_2:
        MOVS     R1,#+1
        MOVS     R0,#+2
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  153       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
        MOVS     R1,#+0
        MOVS     R0,#+2
??TIM_DeInit_10:
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
        POP      {PC}
//  154       break;
//  155  
//  156     case TIM4_BASE:
//  157       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
??TIM_DeInit_3:
        MOVS     R1,#+1
        MOVS     R0,#+4
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  158       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
        MOVS     R1,#+0
        MOVS     R0,#+4
        B.N      ??TIM_DeInit_10
//  159       break;
//  160       
//  161     case TIM5_BASE:
//  162       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
??TIM_DeInit_4:
        MOVS     R1,#+1
        MOVS     R0,#+8
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  163       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
        MOVS     R1,#+0
        MOVS     R0,#+8
        B.N      ??TIM_DeInit_10
//  164       break;
//  165       
//  166     case TIM6_BASE:
//  167       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
??TIM_DeInit_5:
        MOVS     R1,#+1
        MOVS     R0,#+16
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  168       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
        MOVS     R1,#+0
        MOVS     R0,#+16
        B.N      ??TIM_DeInit_10
//  169       break;
//  170       
//  171     case TIM7_BASE:
//  172       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
??TIM_DeInit_6:
        MOVS     R1,#+1
        MOVS     R0,#+32
        _BLF     RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
//  173       RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
        MOVS     R1,#+0
        MOVS     R0,#+32
        B.N      ??TIM_DeInit_10
//  174       break;
//  175       
//  176     case TIM8_BASE:
//  177       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
??TIM_DeInit_8:
        MOVS     R1,#+1
        LSLS     R0,R1,#+13
        _BLF     RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
//  178       RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);  
        MOVS     R1,#+0
        MOVS     R0,#+8192
??TIM_DeInit_9:
        _BLF     RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
//  179       break; 
//  180       
//  181     default:
//  182       break;
//  183   }
//  184 }
        POP      {PC}             ;; return
        Nop      
        DATA
??TIM_DeInit_1:
        DC32     0x40000400
        DC32     0x40000800
        DC32     0x40000c00
        DC32     0x40001000
        DC32     0x40001400
        CFI EndBlock cfiBlock0
//  185 
//  186 /*******************************************************************************
//  187 * Function Name  : TIM_TimeBaseInit
//  188 * Description    : Initializes the TIMx Time Base Unit peripheral according to 
//  189 *                  the specified parameters in the TIM_TimeBaseInitStruct.
//  190 * Input          : - TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM 
//  191 *                    peripheral.
//  192 *                  - TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
//  193 *                   structure that contains the configuration information for
//  194 *                   the specified TIM peripheral.
//  195 * Output         : None
//  196 * Return         : None
//  197 *******************************************************************************/

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock1 Using cfiCommon0
        CFI Function TIM_TimeBaseInit
        THUMB
//  198 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
//  199 {
TIM_TimeBaseInit:
        PUSH     {R4,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R4 Frame(CFA, -8)
        CFI CFA R13+8
//  200   /* Check the parameters */
//  201   assert_param(IS_TIM_123458_PERIPH(TIMx)); 
//  202   assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
//  203   assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
//  204 
//  205   /* Select the Counter Mode and set the clock division */
//  206   TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
        LDRH     R2,[R0, #+0]
        ANDS     R2,R2,#0x8F
        STRH     R2,[R0, #+0]
//  207   TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
//  208                 TIM_TimeBaseInitStruct->TIM_CounterMode;
        LDRH     R2,[R0, #+0]
        LDRH     R3,[R1, #+6]
        LDRH     R4,[R1, #+2]
        ORRS     R4,R4,R3
        ORRS     R4,R4,R2
        STRH     R4,[R0, #+0]
//  209   /* Set the Autoreload value */
//  210   TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
        LDRH     R2,[R1, #+4]
        STRH     R2,[R0, #+44]
//  211 
//  212   /* Set the Prescaler value */
//  213   TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
        LDRH     R2,[R1, #+0]
        STRH     R2,[R0, #+40]
//  214 
//  215   /* Generate an update event to reload the Prescaler value immediatly */
//  216   TIMx->EGR = TIM_PSCReloadMode_Immediate;
        MOVS     R2,#+1
        STRH     R2,[R0, #+20]
//  217     
//  218   if (((*(u32*)&TIMx) == TIM1_BASE) || ((*(u32*)&TIMx) == TIM8_BASE))  
        LDR.N    R2,??DataTable27  ;; 0x40012c00
        CMP      R0,R2
        BEQ.N    ??TIM_TimeBaseInit_0
        LDR.N    R2,??DataTable28  ;; 0x40013400
        CMP      R0,R2
        BNE.N    ??TIM_TimeBaseInit_1
//  219   {