📄 stm32f10x_gpio.s79
字号:
BX LR ;; return
CFI EndBlock cfiBlock12
// 435
// 436 /*******************************************************************************
// 437 * Function Name : GPIO_EventOutputConfig
// 438 * Description : Selects the GPIO pin used as Event output.
// 439 * Input : - GPIO_PortSource: selects the GPIO port to be used as source
// 440 * for Event output.
// 441 * This parameter can be GPIO_PortSourceGPIOx where x can be
// 442 * (A..E).
// 443 * - GPIO_PinSource: specifies the pin for the Event output.
// 444 * This parameter can be GPIO_PinSourcex where x can be (0..15).
// 445 * Output : None
// 446 * Return : None
// 447 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock13 Using cfiCommon0
CFI Function GPIO_EventOutputConfig
THUMB
// 448 void GPIO_EventOutputConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
// 449 {
// 450 u32 tmpreg = 0x00;
// 451
// 452 /* Check the parameters */
// 453 assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
// 454 assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
// 455
// 456 tmpreg = AFIO->EVCR;
GPIO_EventOutputConfig:
LDR.N R2,??GPIO_EventOutputConfig_0 ;; 0x40010000
PUSH {R4,LR}
CFI ?RET Frame(CFA, -4)
CFI R4 Frame(CFA, -8)
CFI CFA R13+8
// 457 /* Clear the PORT[6:4] and PIN[3:0] bits */
// 458 tmpreg &= EVCR_PORTPINCONFIG_MASK;
// 459 tmpreg |= (u32)GPIO_PortSource << 0x04;
// 460 tmpreg |= GPIO_PinSource;
// 461
// 462 AFIO->EVCR = tmpreg;
LDR.N R4,??GPIO_EventOutputConfig_0+0x4 ;; 0xff80
LDR R3,[R2, #+0]
ANDS R4,R4,R3
ORRS R0,R4,R0, LSL #+4
ORRS R1,R1,R0
STR R1,[R2, #+0]
// 463 }
POP {R4,PC} ;; return
DATA
??GPIO_EventOutputConfig_0:
DC32 0x40010000
DC32 0xff80
CFI EndBlock cfiBlock13
// 464
// 465 /*******************************************************************************
// 466 * Function Name : GPIO_EventOutputCmd
// 467 * Description : Enables or disables the Event Output.
// 468 * Input : - NewState: new state of the Event output.
// 469 * This parameter can be: ENABLE or DISABLE.
// 470 * Output : None
// 471 * Return : None
// 472 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock14 Using cfiCommon0
CFI Function GPIO_EventOutputCmd
THUMB
// 473 void GPIO_EventOutputCmd(FunctionalState NewState)
// 474 {
// 475 /* Check the parameters */
// 476 assert_param(IS_FUNCTIONAL_STATE(NewState));
// 477
// 478 *(vu32 *) EVCR_EVOE_BB = (u32)NewState;
GPIO_EventOutputCmd:
LDR.N R1,??GPIO_EventOutputCmd_0 ;; 0x4220001c
STR R0,[R1, #+0]
// 479 }
BX LR ;; return
Nop
DATA
??GPIO_EventOutputCmd_0:
DC32 0x4220001c
CFI EndBlock cfiBlock14
// 480
// 481 /*******************************************************************************
// 482 * Function Name : GPIO_PinRemapConfig
// 483 * Description : Changes the mapping of the specified pin.
// 484 * Input : - GPIO_Remap: selects the pin to remap.
// 485 * This parameter can be one of the following values:
// 486 * - GPIO_Remap_SPI1
// 487 * - GPIO_Remap_I2C1
// 488 * - GPIO_Remap_USART1
// 489 * - GPIO_Remap_USART2
// 490 * - GPIO_PartialRemap_USART3
// 491 * - GPIO_FullRemap_USART3
// 492 * - GPIO_PartialRemap_TIM1
// 493 * - GPIO_FullRemap_TIM1
// 494 * - GPIO_PartialRemap1_TIM2
// 495 * - GPIO_PartialRemap2_TIM2
// 496 * - GPIO_FullRemap_TIM2
// 497 * - GPIO_PartialRemap_TIM3
// 498 * - GPIO_FullRemap_TIM3
// 499 * - GPIO_Remap_TIM4
// 500 * - GPIO_Remap1_CAN
// 501 * - GPIO_Remap2_CAN
// 502 * - GPIO_Remap_PD01
// 503 * - GPIO_Remap_TIM5CH4_LSI
// 504 * - GPIO_Remap_ADC1_ETRGINJ
// 505 * - GPIO_Remap_ADC1_ETRGREG
// 506 * - GPIO_Remap_ADC2_ETRGINJ
// 507 * - GPIO_Remap_ADC2_ETRGREG
// 508 * - GPIO_Remap_SWJ_NoJTRST
// 509 * - GPIO_Remap_SWJ_JTAGDisable
// 510 * - GPIO_Remap_SWJ_Disable
// 511 * - NewState: new state of the port pin remapping.
// 512 * This parameter can be: ENABLE or DISABLE.
// 513 * Output : None
// 514 * Return : None
// 515 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock15 Using cfiCommon0
CFI Function GPIO_PinRemapConfig
THUMB
// 516 void GPIO_PinRemapConfig(u32 GPIO_Remap, FunctionalState NewState)
// 517 {
// 518 u32 tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
// 519
// 520 /* Check the parameters */
// 521 assert_param(IS_GPIO_REMAP(GPIO_Remap));
// 522 assert_param(IS_FUNCTIONAL_STATE(NewState));
// 523
// 524 tmpreg = AFIO->MAPR;
GPIO_PinRemapConfig:
LDR.N R2,??GPIO_PinRemapConfig_0 ;; 0x40010004
PUSH {R4-R6,LR}
CFI ?RET Frame(CFA, -4)
CFI R6 Frame(CFA, -8)
CFI R5 Frame(CFA, -12)
CFI R4 Frame(CFA, -16)
CFI CFA R13+16
// 525
// 526 tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
ANDS R4,R0,#0xF0000
LDR R3,[R2, #+0]
LSRS R5,R4,#+16
// 527 tmp = GPIO_Remap & LSB_MASK;
UXTH R4,R0
// 528
// 529 if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
ANDS R6,R0,#0x300000
CMP R6,#+3145728
BNE.N ??GPIO_PinRemapConfig_1
// 530 {
// 531 tmpreg &= DBGAFR_SWJCFG_MASK;
// 532 AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
LDR R6,[R2, #+0]
MVNS R5,#+251658240
ANDS R3,R3,R5
ANDS R5,R5,R6
STR R5,[R2, #+0]
B.N ??GPIO_PinRemapConfig_2
// 533 }
// 534 else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
??GPIO_PinRemapConfig_1:
LSLS R6,R0,#+11
BPL.N ??GPIO_PinRemapConfig_3
// 535 {
// 536 tmp1 = ((u32)0x03) << tmpmask;
// 537 tmpreg &= ~tmp1;
// 538 tmpreg |= ~DBGAFR_SWJCFG_MASK;
MOVS R6,#+3
LSLS R6,R6,R5
BICS R3,R3,R6
ORRS R3,R3,#0xF000000
B.N ??GPIO_PinRemapConfig_2
// 539 }
// 540 else
// 541 {
// 542 tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
// 543 tmpreg |= ~DBGAFR_SWJCFG_MASK;
??GPIO_PinRemapConfig_3:
LSRS R5,R0,#+21
LSLS R5,R5,#+4
LSLS R5,R4,R5
BICS R3,R3,R5
ORRS R3,R3,#0xF000000
// 544 }
// 545
// 546 if (NewState != DISABLE)
??GPIO_PinRemapConfig_2:
CBZ R1,??GPIO_PinRemapConfig_4
// 547 {
// 548 tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
MOVS R1,R3
MOVS R3,R4
LSRS R0,R0,#+21
LSLS R0,R0,#+4
LSLS R3,R3,R0
ORRS R3,R3,R1
// 549 }
// 550
// 551 AFIO->MAPR = tmpreg;
??GPIO_PinRemapConfig_4:
STR R3,[R2, #+0]
// 552 }
POP {R4-R6,PC} ;; return
Nop
DATA
??GPIO_PinRemapConfig_0:
DC32 0x40010004
CFI EndBlock cfiBlock15
// 553
// 554 /*******************************************************************************
// 555 * Function Name : GPIO_EXTILineConfig
// 556 * Description : Selects the GPIO pin used as EXTI Line.
// 557 * Input : - GPIO_PortSource: selects the GPIO port to be used as
// 558 * source for EXTI lines.
// 559 * This parameter can be GPIO_PortSourceGPIOx where x can be
// 560 * (A..G).
// 561 * - GPIO_PinSource: specifies the EXTI line to be configured.
// 562 * This parameter can be GPIO_PinSourcex where x can be (0..15).
// 563 * Output : None
// 564 * Return : None
// 565 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock16 Using cfiCommon0
CFI Function GPIO_EXTILineConfig
THUMB
// 566 void GPIO_EXTILineConfig(u8 GPIO_PortSource, u8 GPIO_PinSource)
// 567 {
GPIO_EXTILineConfig:
LDR.N R3,??GPIO_EXTILineConfig_0 ;; 0x40010008
ASRS R2,R1,#+2
PUSH {R4,LR}
CFI ?RET Frame(CFA, -4)
CFI R4 Frame(CFA, -8)
CFI CFA R13+8
ADDS R2,R3,R2, LSL #+2
LDR R3,[R2, #+0]
LSLS R1,R1,#+30
LSRS R1,R1,#+28
MOVS R4,#+15
LSLS R4,R4,R1
BICS R3,R3,R4
STR R3,[R2, #+0]
// 568 u32 tmp = 0x00;
// 569
// 570 /* Check the parameters */
// 571 assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
// 572 assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
// 573
// 574 tmp = ((u32)0x0F) << (0x04 * (GPIO_PinSource & (u8)0x03));
// 575
// 576 AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
// 577 AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((u32)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (u8)0x03)));
LDR R3,[R2, #+0]
LSLS R0,R0,R1
ORRS R0,R0,R3
STR R0,[R2, #+0]
// 578 }
POP {R4,PC} ;; return
Nop
DATA
??GPIO_EXTILineConfig_0:
DC32 0x40010008
CFI EndBlock cfiBlock16
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock17 Using cfiCommon0
CFI NoFunction
THUMB
??RCC_APB2PeriphResetCmd??rT:
LDR.N R3,??Subroutine0_0 ;; RCC_APB2PeriphResetCmd
BX R3
DATA
??Subroutine0_0:
DC32 RCC_APB2PeriphResetCmd
CFI EndBlock cfiBlock17
END
// 579
// 580 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
//
// 640 bytes in segment CODE
//
// 632 bytes of CODE memory (+ 8 bytes shared)
//
//Errors: none
//Warnings: none
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