📄 stm32f10x_gpio.s79
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//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32 EVALUATION 10/Nov/2008 11:44:02 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = thumb /
// Endian = little /
// Stack alignment = 4 /
// Source file = D:\资料\ST\ST\usb\FWLib\library\src\stm32f10x_gpio. /
// c /
// Command line = D:\资料\ST\ST\usb\FWLib\library\src\stm32f10x_gpio. /
// c -D VECT_TAB_FLASH -D USE_STM3210E_EVAL -lA /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\STM3210E-EVAL\List\ -o /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\STM3210E-EVAL\Obj\ -z9 --debug /
// --cpu_mode thumb --endian little --cpu cortex-M3 /
// --stack_align 4 --require_prototypes --fpu None /
// --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench 4.0 /
// Evaluation\arm\LIB\dl7mptnnl8f.h" -I /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\..\..\include\ -I /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\..\..\..\..\library\inc\ -I /
// D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\..\..\..\..\..\FWLib\library\inc\ -I /
// "C:\Program Files\IAR Systems\Embedded Workbench /
// 4.0 Evaluation\arm\INC\" --inline_threshold=2 /
// List file = D:\资料\ST\ST\usb\USBLib\demos\Virtual_COM_Port\pro /
// ject\EWARMv4\STM3210E-EVAL\List\stm32f10x_gpio.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME stm32f10x_gpio
RTMODEL "StackAlign4", "USED"
RTMODEL "__cpu_mode", "__pcs__thumb"
RTMODEL "__data_model", "absolute"
RTMODEL "__endian", "little"
RTMODEL "__rt_version", "6"
RSEG CSTACK:DATA:NOROOT(2)
MULTWEAK ??RCC_APB2PeriphResetCmd??rT
PUBLIC GPIO_AFIODeInit
FUNCTION GPIO_AFIODeInit,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC GPIO_DeInit
FUNCTION GPIO_DeInit,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC GPIO_EXTILineConfig
FUNCTION GPIO_EXTILineConfig,0203H
LOCFRAME CSTACK, 8, STACK
PUBLIC GPIO_EventOutputCmd
FUNCTION GPIO_EventOutputCmd,0203H
PUBLIC GPIO_EventOutputConfig
FUNCTION GPIO_EventOutputConfig,0203H
LOCFRAME CSTACK, 8, STACK
PUBLIC GPIO_Init
FUNCTION GPIO_Init,0203H
LOCFRAME CSTACK, 28, STACK
PUBLIC GPIO_PinLockConfig
FUNCTION GPIO_PinLockConfig,0203H
PUBLIC GPIO_PinRemapConfig
FUNCTION GPIO_PinRemapConfig,0203H
LOCFRAME CSTACK, 16, STACK
PUBLIC GPIO_ReadInputData
FUNCTION GPIO_ReadInputData,0203H
PUBLIC GPIO_ReadInputDataBit
FUNCTION GPIO_ReadInputDataBit,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC GPIO_ReadOutputData
FUNCTION GPIO_ReadOutputData,0203H
PUBLIC GPIO_ReadOutputDataBit
FUNCTION GPIO_ReadOutputDataBit,0203H
LOCFRAME CSTACK, 4, STACK
PUBLIC GPIO_ResetBits
FUNCTION GPIO_ResetBits,0203H
PUBLIC GPIO_SetBits
FUNCTION GPIO_SetBits,0203H
PUBLIC GPIO_StructInit
FUNCTION GPIO_StructInit,0203H
PUBLIC GPIO_Write
FUNCTION GPIO_Write,0203H
PUBLIC GPIO_WriteBit
FUNCTION GPIO_WriteBit,0203H
CFI Names cfiNames0
CFI StackFrame CFA R13 HUGEDATA
CFI Resource R0:32, R1:32, R2:32, R3:32, R4:32, R5:32, R6:32, R7:32
CFI Resource R8:32, R9:32, R10:32, R11:32, R12:32, R13:32, R14:32
CFI VirtualResource ?RET:32
CFI EndNames cfiNames0
CFI Common cfiCommon0 Using cfiNames0
CFI CodeAlign 2
CFI DataAlign 4
CFI ReturnAddress ?RET CODE
CFI CFA R13+0
CFI R0 Undefined
CFI R1 Undefined
CFI R2 Undefined
CFI R3 Undefined
CFI R4 SameValue
CFI R5 SameValue
CFI R6 SameValue
CFI R7 SameValue
CFI R8 SameValue
CFI R9 SameValue
CFI R10 SameValue
CFI R11 SameValue
CFI R12 Undefined
CFI R14 Undefined
CFI ?RET R14
CFI EndCommon cfiCommon0
RCC_APB2PeriphResetCmd SYMBOL "RCC_APB2PeriphResetCmd"
??RCC_APB2PeriphResetCmd??rT SYMBOL "??rT", RCC_APB2PeriphResetCmd
EXTERN RCC_APB2PeriphResetCmd
FUNCTION RCC_APB2PeriphResetCmd,0202H
// D:\资料\ST\ST\usb\FWLib\library\src\stm32f10x_gpio.c
// 1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
// 2 * File Name : stm32f10x_gpio.c
// 3 * Author : MCD Application Team
// 4 * Version : V2.0.1
// 5 * Date : 06/13/2008
// 6 * Description : This file provides all the GPIO firmware functions.
// 7 ********************************************************************************
// 8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
// 9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
// 10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
// 11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
// 12 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
// 13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
// 14 *******************************************************************************/
// 15
// 16 /* Includes ------------------------------------------------------------------*/
// 17 #include "stm32f10x_gpio.h"
// 18 #include "stm32f10x_rcc.h"
// 19
// 20 /* Private typedef -----------------------------------------------------------*/
// 21 /* Private define ------------------------------------------------------------*/
// 22 /* ------------ RCC registers bit address in the alias region ----------- */
// 23 #define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
// 24
// 25 /* --- EVENTCR Register ---*/
// 26 /* Alias word address of EVOE bit */
// 27 #define EVCR_OFFSET (AFIO_OFFSET + 0x00)
// 28 #define EVOE_BitNumber ((u8)0x07)
// 29 #define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
// 30
// 31 #define EVCR_PORTPINCONFIG_MASK ((u16)0xFF80)
// 32 #define LSB_MASK ((u16)0xFFFF)
// 33 #define DBGAFR_POSITION_MASK ((u32)0x000F0000)
// 34 #define DBGAFR_SWJCFG_MASK ((u32)0xF0FFFFFF)
// 35 #define DBGAFR_LOCATION_MASK ((u32)0x00200000)
// 36 #define DBGAFR_NUMBITS_MASK ((u32)0x00100000)
// 37
// 38 /* Private macro -------------------------------------------------------------*/
// 39 /* Private variables ---------------------------------------------------------*/
// 40 /* Private function prototypes -----------------------------------------------*/
// 41 /* Private functions ---------------------------------------------------------*/
// 42
// 43 /*******************************************************************************
// 44 * Function Name : GPIO_DeInit
// 45 * Description : Deinitializes the GPIOx peripheral registers to their default
// 46 * reset values.
// 47 * Input : - GPIOx: where x can be (A..G) to select the GPIO peripheral.
// 48 * Output : None
// 49 * Return : None
// 50 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock0 Using cfiCommon0
CFI Function GPIO_DeInit
THUMB
// 51 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
// 52 {
// 53 /* Check the parameters */
// 54 assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
// 55
// 56 switch (*(u32*)&GPIOx)
GPIO_DeInit:
LDR.N R1,??GPIO_DeInit_0 ;; 0x40010800
PUSH {LR}
CFI ?RET Frame(CFA, -4)
CFI CFA R13+4
CMP R0,R1
BEQ.N ??GPIO_DeInit_1
LDR.N R1,??GPIO_DeInit_0+0x4 ;; 0x40010c00
CMP R0,R1
BEQ.N ??GPIO_DeInit_2
LDR.N R1,??GPIO_DeInit_0+0x8 ;; 0x40011000
CMP R0,R1
BEQ.N ??GPIO_DeInit_3
LDR.N R1,??GPIO_DeInit_0+0xC ;; 0x40011400
CMP R0,R1
BEQ.N ??GPIO_DeInit_4
LDR.N R1,??GPIO_DeInit_0+0x10 ;; 0x40011800
CMP R0,R1
BEQ.N ??GPIO_DeInit_5
LDR.N R1,??GPIO_DeInit_0+0x14 ;; 0x40011c00
CMP R0,R1
BEQ.N ??GPIO_DeInit_6
LDR.N R1,??GPIO_DeInit_0+0x18 ;; 0x40012000
CMP R0,R1
BEQ.N ??GPIO_DeInit_7
POP {PC}
// 57 {
// 58 case GPIOA_BASE:
// 59 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
??GPIO_DeInit_1:
MOVS R1,#+1
MOVS R0,#+4
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
// 60 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
MOVS R1,#+0
MOVS R0,#+4
B.N ??GPIO_DeInit_8
// 61 break;
// 62
// 63 case GPIOB_BASE:
// 64 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
??GPIO_DeInit_2:
MOVS R1,#+1
MOVS R0,#+8
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
// 65 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
MOVS R1,#+0
MOVS R0,#+8
??GPIO_DeInit_8:
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
POP {PC}
// 66 break;
// 67
// 68 case GPIOC_BASE:
// 69 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
??GPIO_DeInit_3:
MOVS R1,#+1
MOVS R0,#+16
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
// 70 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
MOVS R1,#+0
MOVS R0,#+16
B.N ??GPIO_DeInit_8
// 71 break;
// 72
// 73 case GPIOD_BASE:
// 74 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
??GPIO_DeInit_4:
MOVS R1,#+1
MOVS R0,#+32
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
// 75 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
MOVS R1,#+0
MOVS R0,#+32
B.N ??GPIO_DeInit_8
// 76 break;
// 77
// 78 case GPIOE_BASE:
// 79 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
??GPIO_DeInit_5:
MOVS R1,#+1
MOVS R0,#+64
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
// 80 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
MOVS R1,#+0
MOVS R0,#+64
B.N ??GPIO_DeInit_8
// 81 break;
// 82
// 83 case GPIOF_BASE:
// 84 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
??GPIO_DeInit_6:
MOVS R1,#+1
MOVS R0,#+128
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
// 85 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
MOVS R1,#+0
MOVS R0,#+128
B.N ??GPIO_DeInit_8
// 86 break;
// 87
// 88 case GPIOG_BASE:
// 89 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
??GPIO_DeInit_7:
MOVS R1,#+1
LSLS R0,R1,#+8
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
// 90 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
MOVS R1,#+0
MOVS R0,#+256
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