📄 mci_lpc23xx.c
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}
/*--------------------------- mci_cmd_write_block ---------------------------*/
static BOOL mci_cmd_write_block (U32 block, U32 cnt) {
/* Send a command to Write Single/Multiple block. */
U32 i,rstat,rval;
U8 cmd;
cmd = WRITE_BLOCK;
if (cnt > 1) {
cmd = WRITE_MULT_BLOCK;
}
block *= 512;
for (i = 0; i < 20; i++) {
rstat = mci_command (cmd, block, RESP_SHORT, &rval);
if (rstat == 0 && (rval & 0x0F00) == 0x0900) {
/* Ready and in TRAN state. */
return (__TRUE);
}
}
return (__FALSE);
}
/*--------------------------- mci_read_status -------------------------------*/
static U32 mci_read_status (void) {
/* Read the status of Flash Card. */
U32 i,arg,rstat,rval;
arg = 0x00010000;
if (CardType == CARD_SD) {
/* Use address from SET_RELATIVE_ADDR. */
arg = CardRCA << 16;
}
for (i = 0; i < 200; i++) {
rstat = mci_command (SEND_STATUS, arg, RESP_SHORT, &rval);
if (rstat == 0 && (rval & 0x0100)) {
/* The Ready bit should be set, state TRAN or RCV. */
return (rval);
}
}
return (MCI_RESP_INVALID);
}
/*--------------------------- mci_send_stop ---------------------------------*/
static BOOL mci_send_stop (void) {
/* Stop transmission, Flash Card is in wrong state. */
U32 i,rstat,rval;
for (i = 0; i < 20; i++) {
rstat = mci_command (STOP_TRANSMISSION, 0, RESP_SHORT, &rval);
if (rstat == 0 && (rval & 0x0100)) {
/* The Ready bit should be set. */
return (__TRUE);
}
}
return (__FALSE);
}
/*--------------------------- mci_wait_for_tran -----------------------------*/
static BOOL mci_wait_for_tran (void) {
/* Wait for Card state TRAN. */
U32 i;
for (i = WR_TOUT; i; i--) {
/* Wait for Card state TRAN to continue. */
if ((mci_read_status () & 0x0F00) == 0x0900) {
break;
}
}
if (i == 0) {
/* Previous request has Failed. */
mci_send_stop ();
return (__FALSE);
}
return (__TRUE);
}
/*--------------------------- mmc_command -----------------------------------*/
static U32 mci_command (U8 cmd, U32 arg, U32 resp_type, U32 *rp) {
/* Send a Command to Flash card and get a Response. */
U32 cmdval,stat;
cmd &= 0x3F;
cmdval = 0x400 | cmd;
switch (resp_type) {
case RESP_SHORT:
cmdval |= 0x40;
break;
case RESP_LONG:
cmdval |= 0xC0;
break;
}
/* Send the command. */
MCI_ARGUMENT = arg;
MCI_COMMAND = cmdval;
if (resp_type == RESP_NONE) {
/* Wait until command finished. */
while (MCI_STATUS & MCI_CMD_ACTIVE);
MCI_CLEAR = 0x7FF;
return (0);
}
for (;;) {
stat = MCI_STATUS;
if (stat & MCI_CMD_TIMEOUT) {
MCI_CLEAR = stat & MCI_CLEAR_MASK;
return (stat);
}
if (stat & MCI_CMD_CRC_FAIL) {
MCI_CLEAR = stat & MCI_CLEAR_MASK;
if ((cmd == SEND_OP_COND) ||
(cmd == SEND_APP_OP_COND) ||
(cmd == STOP_TRANSMISSION)) {
MCI_COMMAND = 0;
break;
}
return (stat);
}
if (stat & MCI_CMD_RESP_END) {
MCI_CLEAR = stat & MCI_CLEAR_MASK;
break;
}
}
if ((MCI_RESP_CMD & 0x3F) != cmd) {
if ((cmd != SEND_OP_COND) &&
(cmd != SEND_APP_OP_COND) &&
(cmd != ALL_SEND_CID) &&
(cmd != SEND_CSD)) {
return (MCI_RESP_INVALID);
}
}
if (rp == NULL) {
/* Response pointer undefined. */
return (MCI_RESP_INVALID);
}
/* Read MCI response registers */
rp[0] = MCI_RESP0;
if (resp_type == RESP_LONG) {
rp[1] = MCI_RESP1;
rp[2] = MCI_RESP2;
rp[3] = MCI_RESP3;
}
return (0);
}
/*--------------------------- mci_dma_start ---------------------------------*/
static void mci_dma_start (U32 mode, U8 *buf) {
/* Configure DMA controller Ch0 for read or write. */
if (mode == DMA_READ) {
/* Transfer from MCI-FIFO to memory. */
GPDMA_CH0_SRC = (U32)&MCI_FIFO;
GPDMA_CH0_DEST = (U32)buf;
/* The burst size set to 8, transfer size 512 bytes. */
GPDMA_CH0_CTRL = (512 >> 2) | (0x02 << 12) | (0x02 << 15) |
(0x02 << 18) | (0x02 << 21) | (1 << 27) | (1u << 31);
GPDMA_CH0_CFG = 0x10001 | (0x04 << 1) | (0x00 << 6) | (0x06 << 11);
}
else {
/* Transfer from memory to MCI-FIFO. */
GPDMA_CH0_SRC = (U32)buf;
GPDMA_CH0_DEST = (U32)&MCI_FIFO;
/* The burst size set to 8, transfer size 512 bytes. */
GPDMA_CH0_CTRL = (512 >> 2) | (0x02 << 12) | (0x02 << 15) |
(0x02 << 18) | (0x02 << 21) | (1 << 26) | (1u << 31);
GPDMA_CH0_CFG = 0x10001 | (0x00 << 1) | (0x04 << 6) | (0x05 << 11);
}
/* Enable DMA channels, little endian */
GPDMA_INT_TCCLR = 0x01;
GPDMA_CONFIG = 0x01;
}
/*--------------------------- mci_read_sect ---------------------------------*/
BOOL mci_read_sect (U32 sect, U8 *buf, U32 cnt) {
/* Read one or more 512 byte sectors from Flash Card. */
U32 i;
if (mci_wait_for_tran () == __FALSE) {
/* Card not in TRAN state. */
return (__FALSE);
}
if (mci_cmd_read_block (sect, cnt) == __FALSE) {
/* Command Failed. */
return (__FALSE);
}
/* Set MCI Transfer registers. */
MCI_DATA_TMR = DATA_RD_TOUT_VALUE;
MCI_DATA_LEN = cnt * 512;
/* Start DMA Peripheral to Memory transfer. */
mci_dma_start (DMA_READ, buf);
MCI_DATA_CTRL = 0x9B;
for (i = DMA_TOUT; i; i--) {
if (GPDMA_RAW_INT_TCSTAT & 0x01) {
/* Data transfer finished. */
break;
}
}
if (i == 0) {
/* DMA Transfer timeout. */
return (__FALSE);
}
if (cnt > 1) {
/* Stop reading Multiple sectors. */
mci_send_stop ();
}
return (__TRUE);
}
/*--------------------------- mci_write_sect --------------------------------*/
BOOL mci_write_sect (U32 sect, U8 *buf, U32 cnt) {
/* Write a 512 byte sector to Flash Card. */
U32 i,j;
if (mci_wait_for_tran () == __FALSE) {
/* Card not in TRAN state. */
return (__FALSE);
}
if (mci_cmd_write_block (sect, cnt) == __FALSE) {
/* Command Failed. */
return (__FALSE);
}
for (j = 0; j < cnt; buf += 512, j++) {
/* Set MCI Transfer registers. */
MCI_DATA_TMR = DATA_WR_TOUT_VALUE;
MCI_DATA_LEN = 512;
/* Start DMA Memory to Peripheral transfer. */
mci_dma_start (DMA_WRITE, buf);
MCI_DATA_CTRL = 0x99;
for (i = DMA_TOUT; i; i--) {
if (GPDMA_RAW_INT_TCSTAT & 0x01) {
/* Data transfer finished. */
break;
}
}
if (i == 0) {
/* DMA Data Transfer timeout. */
mci_send_stop ();
/* Write request Failed. */
return (__FALSE);
}
if (cnt == 1) {
return (__TRUE);
}
/* Wait until Data Block sent to Card. */
while (MCI_STATUS != (MCI_DATA_END | MCI_DATA_BLK_END)) {
if (MCI_STATUS & (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT)) {
/* If error while Data Block sending occured. */
mci_send_stop ();
/* Write request Failed. */
return (__FALSE);
}
}
for (i = WR_TOUT; i; i--) {
if ((mci_read_status () & 0x0F00) == 0x0D00) {
/* Buffer available for further sending, card state RCV. */
break;
}
}
}
mci_send_stop ();
/* Write request Ok. */
return (__TRUE);
}
/*--------------------------- mci_read_config -------------------------------*/
BOOL mci_read_config (MMCFG *cfg) {
/* Read MMC/SD Card device configuration. */
U32 i,rstat,arg,v,m,rval[4];
/* Wait if potential Write in progress. */
mci_wait_for_tran ();
/* Deselect the Card, transit to STBY state. */
mci_command (SELECT_CARD, 0, RESP_NONE, NULL);
/* Read the CID - Card Identification. */
cfg->sernum = sernum;
/* Read the CSD - Card Specific Data. */
arg = 0x00010000;
if (CardType == CARD_SD) {
/* Use address from SET_RELATIVE_ADDR. */
arg = CardRCA << 16;
}
for (i = 20; i; i--) {
rstat = mci_command (SEND_CSD, arg, RESP_LONG, &rval[0]);
if (rstat == 0) {
/* Response is back and correct. */
break;
}
}
if (i == 0) {
/* Read CSD failed. */
return (__FALSE);
}
/* Read Block length. */
v = (rval[1] >> 16) & 0x0F;
cfg->read_blen = 1 << v;
/* Write Block length */
v = (rval[3] >> 22) & 0x0F;
cfg->write_blen = 1 << v;
/* Total Number of blocks */
v = ((rval[1] << 2) | (rval[2] >> 30)) & 0x0FFF;
m = (rval[2] >> 15) & 0x07;
cfg->blocknr = (v + 1) << (m + 2);
/* Re-select the Card, back to TRAN state. */
return (mci_select_card ());
}
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/
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