📄 main.txt
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;;;769 return;
;;;770 }
000be0 e12fff1e BX lr
;;;771
ENDP
reset_timer PROC
;;;784
;;;785 if ( timer_num == 0 )
000be4 e3500000 CMP r0,#0
000be8 1a000004 BNE |L1.3072|
;;;786 {
;;;787 regVal = T0TCR;
000bec e59f229c LDR r2,|L1.3728|
000bf0 e5921004 LDR r1,[r2,#4]
;;;788 regVal |= 0x02;
000bf4 e3811002 ORR r1,r1,#2
;;;789 T0TCR = regVal;
000bf8 e5821004 STR r1,[r2,#4]
000bfc ea000003 B |L1.3088|
|L1.3072|
;;;790 }
;;;791 else
;;;792 {
;;;793 regVal = T1TCR;
000c00 e59f22b4 LDR r2,|L1.3772|
000c04 e5921004 LDR r1,[r2,#4]
;;;794 regVal |= 0x02;
000c08 e3811002 ORR r1,r1,#2
;;;795 T1TCR = regVal;
000c0c e5821004 STR r1,[r2,#4]
|L1.3088|
;;;796 }
;;;797 return;
;;;798 }
000c10 e12fff1e BX lr
;;;799
ENDP
init_timer PROC
;;;811 DWORD init_timer( DWORD TimerInterval )
;;;812 {
000c14 e92d4010 PUSH {r4,lr}
000c18 e1a04000 MOV r4,r0
;;;813 timer_counter = 0;
000c1c e3a00000 MOV r0,#0
000c20 e59f126c LDR r1,|L1.3732|
000c24 e5810000 STR r0,[r1,#0] ; timer_counter
;;;814 T0MR0 = TimerInterval;
000c28 e59f0260 LDR r0,|L1.3728|
000c2c e5804018 STR r4,[r0,#0x18]
;;;815 T0MCR = 3; /* Interrupt and Reset on MR0 */
000c30 e3a00003 MOV r0,#3
000c34 e59f1254 LDR r1,|L1.3728|
000c38 e5810014 STR r0,[r1,#0x14]
;;;816 //if ( install_irq( TIMER0_INT, (void *)Timer0Handler, HIGHEST_PRIORITY ) == FALSE )
;;;817 if ( install_irq( TIMER0_INT, (void *)Timer0Handler, 2 ) == FALSE )
000c3c e3a02002 MOV r2,#2
000c40 e24f1f72 ADR r1,Timer0Handler
000c44 e3a00004 MOV r0,#4
000c48 ebfffffe BL install_irq
000c4c e3500000 CMP r0,#0
000c50 1a000002 BNE |L1.3168|
;;;818 {
;;;819 return (FALSE);
000c54 e3a00000 MOV r0,#0
|L1.3160|
000c58 e8bd4010 POP {r4,lr}
;;;820 }
;;;821 else
;;;822 {
;;;823 return (TRUE);
;;;824 }
;;;825 //return (TRUE);
;;;826 }
000c5c e12fff1e BX lr
|L1.3168|
000c60 e3a00001 MOV r0,#1 ;823
000c64 eafffffb B |L1.3160|
;;;827
ENDP
set_uart0_to_tx_status PROC
;;;830 {
;;;831 FIO4SET=(uint32)0x01<<29;
000c68 e3a00202 MOV r0,#0x20000000
000c6c e59f11cc LDR r1,|L1.3648|
000c70 e5810098 STR r0,[r1,#0x98]
;;;832 }
000c74 e12fff1e BX lr
;;;833
ENDP
set_uart0_to_rx_status PROC
;;;835 {
;;;836 FIO4CLR=(uint32)0x01<<29;
000c78 e3a00202 MOV r0,#0x20000000
000c7c e59f11bc LDR r1,|L1.3648|
000c80 e581009c STR r0,[r1,#0x9c]
;;;837 }
000c84 e12fff1e BX lr
;;;838
ENDP
set_uart1_to_tx_status PROC
;;;842 {
;;;843 FIO4SET=(uint32)0x01<<28;
000c88 e3a00201 MOV r0,#0x10000000
000c8c e59f11ac LDR r1,|L1.3648|
000c90 e5810098 STR r0,[r1,#0x98]
;;;844 }
000c94 e12fff1e BX lr
;;;845
ENDP
set_uart1_to_rx_status PROC
;;;847 {
;;;848 FIO4CLR=(uint32)0x01<<28;
000c98 e3a00201 MOV r0,#0x10000000
000c9c e59f119c LDR r1,|L1.3648|
000ca0 e581009c STR r0,[r1,#0x9c]
;;;849 }
000ca4 e12fff1e BX lr
;;;850
ENDP
set_uart2_to_tx_status PROC
;;;853 {
;;;854 FIO3SET=(uint32)0x01<<26;
000ca8 e3a00301 MOV r0,#0x4000000
000cac e59f118c LDR r1,|L1.3648|
000cb0 e5810078 STR r0,[r1,#0x78]
;;;855 }
000cb4 e12fff1e BX lr
;;;856
ENDP
set_uart2_to_rx_status PROC
;;;858 {
;;;859 FIO3CLR=(uint32)0x01<<26;
000cb8 e3a00301 MOV r0,#0x4000000
000cbc e59f117c LDR r1,|L1.3648|
000cc0 e581007c STR r0,[r1,#0x7c]
;;;860 }
000cc4 e12fff1e BX lr
;;;861
ENDP
set_uart3_to_tx_status PROC
;;;865 {
;;;866 FIO3SET=(uint32)0x01<<25;
000cc8 e3a00402 MOV r0,#0x2000000
000ccc e59f116c LDR r1,|L1.3648|
000cd0 e5810078 STR r0,[r1,#0x78]
;;;867 }
000cd4 e12fff1e BX lr
;;;868
ENDP
set_uart3_to_rx_status PROC
;;;870 {
;;;871 FIO3CLR=(uint32)0x01<<25;
000cd8 e3a00402 MOV r0,#0x2000000
000cdc e59f115c LDR r1,|L1.3648|
000ce0 e581007c STR r0,[r1,#0x7c]
;;;872 }
000ce4 e12fff1e BX lr
;;;873
ENDP
SEND_MODBUS_FRAME PROC
;;;881
;;;882 }
000ce8 e12fff1e BX lr
;;;883
ENDP
feed_watchdog PROC
;;;1424
;;;1425 if(feed_watchdog_flag1==0)
000cec e59f01cc LDR r0,|L1.3776|
000cf0 e5d00000 LDRB r0,[r0,#0] ; feed_watchdog_flag1
000cf4 e3500000 CMP r0,#0
000cf8 1a000006 BNE |L1.3352|
;;;1426 {
;;;1427 feed_watchdog_flag1=1;
000cfc e3a00001 MOV r0,#1
000d00 e59f11b8 LDR r1,|L1.3776|
000d04 e5c10000 STRB r0,[r1,#0] ; feed_watchdog_flag1
;;;1428 IOSET0=(uint32)0x01<<17;
000d08 e3a00802 MOV r0,#0x20000
000d0c e59f1138 LDR r1,|L1.3660|
000d10 e5810004 STR r0,[r1,#4]
000d14 ea000005 B |L1.3376|
|L1.3352|
;;;1429 }
;;;1430 else
;;;1431 {
;;;1432 feed_watchdog_flag1=0;
000d18 e3a00000 MOV r0,#0
000d1c e59f119c LDR r1,|L1.3776|
000d20 e5c10000 STRB r0,[r1,#0] ; feed_watchdog_flag1
;;;1433 IOCLR0=(uint32)0x01<<17;
000d24 e3a00802 MOV r0,#0x20000
000d28 e59f111c LDR r1,|L1.3660|
000d2c e581000c STR r0,[r1,#0xc]
|L1.3376|
;;;1434 }
;;;1435 }
000d30 e12fff1e BX lr
;;;1436
ENDP
Ldelay PROC
;;;884 void Ldelay(unsigned int dly)
;;;885 {
000d34 e52de004 PUSH {lr}
000d38 e1a03000 MOV r3,r0
;;;886 unsigned int i;
;;;887
;;;888 for ( ; dly>0; dly--)
000d3c ea000007 B |L1.3424|
|L1.3392|
;;;889 for (i=0; i<50000; i++)
000d40 e3a02000 MOV r2,#0
000d44 ea000001 B |L1.3408|
|L1.3400|
;;;890 {
;;;891 feed_watchdog();
000d48 ebfffffe BL feed_watchdog
000d4c e2822001 ADD r2,r2,#1 ;889
|L1.3408|
000d50 e59f016c LDR r0,|L1.3780|
000d54 e1520000 CMP r2,r0 ;889
000d58 3afffffa BCC |L1.3400|
000d5c e2433001 SUB r3,r3,#1 ;888
|L1.3424|
000d60 e3530000 CMP r3,#0 ;888
000d64 1afffff5 BNE |L1.3392|
;;;892 }
;;;893 }
000d68 e49de004 POP {lr}
000d6c e12fff1e BX lr
;;;894
ENDP
delay_xus PROC
;;;907 void delay_xus(unsigned int dly)
;;;908 {
000d70 e52de004 PUSH {lr}
000d74 e1a02000 MOV r2,r0
;;;909 for(;dly>0;dly--)
000d78 ea000002 B |L1.3464|
|L1.3452|
;;;910 {
;;;911 delay(200);
000d7c e3a000c8 MOV r0,#0xc8
000d80 ebfffffe BL delay
000d84 e2422001 SUB r2,r2,#1 ;909
|L1.3464|
000d88 e3520000 CMP r2,#0 ;909
000d8c 1afffffa BNE |L1.3452|
;;;912 }
;;;913 }
000d90 e49de004 POP {lr}
000d94 e12fff1e BX lr
;;;914
ENDP
delay_xms PROC
;;;916 void delay_xms(unsigned int dly)
;;;917 {
000d98 e52de004 PUSH {lr}
000d9c e1a03000 MOV r3,r0
;;;918 for(;dly>0;dly--)
000da0 ea000002 B |L1.3504|
|L1.3492|
;;;919 {
;;;920 delay_xus(1000);
000da4 e3a00ffa MOV r0,#0x3e8
000da8 ebfffffe BL delay_xus
000dac e2433001 SUB r3,r3,#1 ;918
|L1.3504|
000db0 e3530000 CMP r3,#0 ;918
000db4 1afffffa BNE |L1.3492|
;;;921 }
;;;922 }
000db8 e49de004 POP {lr}
000dbc e12fff1e BX lr
;;;923
ENDP
i2cstart PROC
;;;968 void i2cstart(void)
;;;969 {
000dc0 e52de004 PUSH {lr}
;;;970 SDA_OUT;
000dc4 e59f0080 LDR r0,|L1.3660|
000dc8 e5900008 LDR r0,[r0,#8]
000dcc e3800302 ORR r0,r0,#0x8000000
000dd0 e59f1074 LDR r1,|L1.3660|
000dd4 e5810008 STR r0,[r1,#8]
000dd8 e3a00ffa MOV r0,#0x3e8
000ddc ebfffffe BL delay
;;;971 SET_SDA;
000de0 e3a00302 MOV r0,#0x8000000
000de4 e59f1060 LDR r1,|L1.3660|
000de8 e5810004 STR r0,[r1,#4]
000dec e3a00ffa MOV r0,#0x3e8
000df0 ebfffffe BL delay
;;;972 delay_xus(10);
000df4 e3a0000a MOV r0,#0xa
000df8 ebfffffe BL delay_xus
;;;973 SET_SCL;
000dfc e3a00201 MOV r0,#0x10000000
000e00 e59f1044 LDR r1,|L1.3660|
000e04 e5810004 STR r0,[r1,#4]
000e08 e3a00ffa MOV r0,#0x3e8
000e0c ebfffffe BL delay
;;;974 CLR_SDA;
000e10 e3a00302 MOV r0,#0x8000000
000e14 e59f1030 LDR r1,|L1.3660|
000e18 e581000c STR r0,[r1,#0xc]
000e1c e3a00ffa MOV r0,#0x3e8
000e20 ebfffffe BL delay
;;;975 CLR_SCL;
000e24 e3a00201 MOV r0,#0x10000000
000e28 e59f101c LDR r1,|L1.3660|
000e2c e581000c STR r0,[r1,#0xc]
000e30 e3a00ffa MOV r0,#0x3e8
000e34 ebfffffe BL delay
;;;976 }
000e38 e49de004 POP {lr}
000e3c e12fff1e BX lr
|L1.3648|
000e40 3fffc000 DCD 0x3fffc000
|L1.3652|
000e44 00000000 DCD key_debounce_flag
|L1.3656|
000e48 00000000 DCD KEY_CODE
|L1.3660|
000e4c e0028000 DCD 0xe0028000
|L1.3664|
000e50 00000000 DCD read_ad_channel_selector
|L1.3668|
000e54 00000000 DCD TEMP_CHANNEL_1_AD_VALUE
|L1.3672|
000e58 00000000 DCD TEMP_CHANNEL_2_AD_VALUE
|L1.3676|
000e5c 00000000 DCD TEMP_CHANNEL_3_AD_VALUE
|L1.3680|
000e60 00000000 DCD TEMP_CHANNEL_4_AD_VALUE
|L1.3684|
000e64 00000000 DCD TEMP_CHANNEL_5_AD_VA⌨️ 快捷键说明
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