📄 uart.txt
字号:
000754 e581000c STR r0,[r1,#0xc] ;429
000758 e3a00007 MOV r0,#7 ;430
00075c e5810008 STR r0,[r1,#8] ;430
000760 e3a02001 MOV r2,#1 ;432
000764 e59f1254 LDR r1,|L1.2496|
000768 e3a0001c MOV r0,#0x1c ;432
00076c ebfffffe BL install_irq
000770 e3500000 CMP r0,#0 ;432
000774 1a000001 BNE |L1.1920|
000778 e3a00000 MOV r0,#0 ;434
00077c eaffffb2 B |L1.1612|
|L1.1920|
000780 e3a00007 MOV r0,#7 ;437
000784 e59f11fc LDR r1,|L1.2440|
000788 e5810004 STR r0,[r1,#4] ;437
00078c e3a00001 MOV r0,#1 ;438
000790 eaffffad B |L1.1612|
|L1.1940|
000794 e3540003 CMP r4,#3 ;441
000798 1a000021 BNE |L1.2084|
00079c e59f020c LDR r0,|L1.2480|
0007a0 e5900000 LDR r0,[r0,#0] ;444
0007a4 e380000a ORR r0,r0,#0xa ;444
0007a8 e59f1200 LDR r1,|L1.2480|
0007ac e5810000 STR r0,[r1,#0] ;444
0007b0 e3a00083 MOV r0,#0x83 ;448
0007b4 e1811081 ORR r1,r1,r1,LSL #1 ;448
0007b8 e581000c STR r0,[r1,#0xc] ;448
0007bc e1a01006 MOV r1,r6 ;449
0007c0 e59f01ec LDR r0,|L1.2484|
0007c4 ebfffffe BL __aeabi_uidivmod
0007c8 e1a05000 MOV r5,r0 ;449
0007cc e1a00425 LSR r0,r5,#8 ;450
0007d0 e59f11c4 LDR r1,|L1.2460|
0007d4 e5810004 STR r0,[r1,#4] ;450
0007d8 e20500ff AND r0,r5,#0xff ;451
0007dc e5810000 STR r0,[r1,#0] ;451
0007e0 e3a00003 MOV r0,#3 ;452
0007e4 e581000c STR r0,[r1,#0xc] ;452
0007e8 e3a00007 MOV r0,#7 ;453
0007ec e5810008 STR r0,[r1,#8] ;453
0007f0 e3a02001 MOV r2,#1 ;455
0007f4 e24f1e3a ADR r1,UART3Handler
0007f8 e3a0001d MOV r0,#0x1d ;455
0007fc ebfffffe BL install_irq
000800 e3500000 CMP r0,#0 ;455
000804 1a000001 BNE |L1.2064|
000808 e3a00000 MOV r0,#0 ;457
00080c eaffff8e B |L1.1612|
|L1.2064|
000810 e3a00007 MOV r0,#7 ;460
000814 e59f1180 LDR r1,|L1.2460|
000818 e5810004 STR r0,[r1,#4] ;460
00081c e3a00001 MOV r0,#1 ;461
000820 eaffff89 B |L1.1612|
|L1.2084|
000824 e3a00000 MOV r0,#0 ;467
000828 eaffff87 B |L1.1612|
;;;469
ENDP
UARTSend PROC
;;;481 {
;;;482 if ( portNum == 0 )
00082c e3500000 CMP r0,#0
000830 1a000010 BNE |L1.2168|
;;;483 {
;;;484 while ( Length != 0 )
000834 ea00000c B |L1.2156|
|L1.2104|
;;;485 {
;;;486 /* THRE status, contain valid data */
;;;487 while ( !(UART0TxEmpty & 0x01) );
000838 e1a00000 MOV r0,r0
|L1.2108|
00083c e59f312c LDR r3,|L1.2416|
000840 e5d33000 LDRB r3,[r3,#0] ; UART0TxEmpty
000844 e3130001 TST r3,#1
000848 0afffffb BEQ |L1.2108|
;;;488 U0THR = *BufferPtr;
00084c e5d13000 LDRB r3,[r1,#0]
000850 e59fc104 LDR r12,|L1.2396|
000854 e58c3000 STR r3,[r12,#0]
;;;489 UART0TxEmpty = 0; /* not empty in the THR until it shifts out */
000858 e3a03000 MOV r3,#0
00085c e59fc10c LDR r12,|L1.2416|
000860 e5cc3000 STRB r3,[r12,#0] ; UART0TxEmpty
;;;490 BufferPtr++;
000864 e2811001 ADD r1,r1,#1
;;;491 Length--;
000868 e2422001 SUB r2,r2,#1
|L1.2156|
00086c e3520000 CMP r2,#0 ;484
000870 1afffff0 BNE |L1.2104|
000874 ea000037 B |L1.2392|
|L1.2168|
;;;492 }
;;;493 }
;;;494 else if(portNum==1)
000878 e3500001 CMP r0,#1
00087c 1a000010 BNE |L1.2244|
;;;495 {
;;;496 while ( Length != 0 )
000880 ea00000c B |L1.2232|
|L1.2180|
;;;497 {
;;;498 /* THRE status, contain valid data */
;;;499 while ( !(UART1TxEmpty & 0x01) );
000884 e1a00000 MOV r0,r0
|L1.2184|
000888 e59f30f4 LDR r3,|L1.2436|
00088c e5d33000 LDRB r3,[r3,#0] ; UART1TxEmpty
000890 e3130001 TST r3,#1
000894 0afffffb BEQ |L1.2184|
;;;500 U1THR = *BufferPtr;
000898 e5d13000 LDRB r3,[r1,#0]
00089c e59fc0d0 LDR r12,|L1.2420|
0008a0 e58c3000 STR r3,[r12,#0]
;;;501 UART1TxEmpty = 0; /* not empty in the THR until it shifts out */
0008a4 e3a03000 MOV r3,#0
0008a8 e59fc0d4 LDR r12,|L1.2436|
0008ac e5cc3000 STRB r3,[r12,#0] ; UART1TxEmpty
;;;502 BufferPtr++;
0008b0 e2811001 ADD r1,r1,#1
;;;503 Length--;
0008b4 e2422001 SUB r2,r2,#1
|L1.2232|
0008b8 e3520000 CMP r2,#0 ;496
0008bc 1afffff0 BNE |L1.2180|
0008c0 ea000024 B |L1.2392|
|L1.2244|
;;;504 }
;;;505 }
;;;506 else if(portNum==2)
0008c4 e3500002 CMP r0,#2
0008c8 1a000010 BNE |L1.2320|
;;;507 {
;;;508 while ( Length != 0 )
0008cc ea00000c B |L1.2308|
|L1.2256|
;;;509 {
;;;510 /* THRE status, contain valid data */
;;;511 while ( !(UART2TxEmpty & 0x01) );
0008d0 e1a00000 MOV r0,r0
|L1.2260|
0008d4 e59f30bc LDR r3,|L1.2456|
0008d8 e5d33000 LDRB r3,[r3,#0] ; UART2TxEmpty
0008dc e3130001 TST r3,#1
0008e0 0afffffb BEQ |L1.2260|
;;;512 U2THR = *BufferPtr;
0008e4 e5d13000 LDRB r3,[r1,#0]
0008e8 e59fc098 LDR r12,|L1.2440|
0008ec e58c3000 STR r3,[r12,#0]
;;;513 UART2TxEmpty = 0; /* not empty in the THR until it shifts out */
0008f0 e3a03000 MOV r3,#0
0008f4 e59fc09c LDR r12,|L1.2456|
0008f8 e5cc3000 STRB r3,[r12,#0] ; UART2TxEmpty
;;;514 BufferPtr++;
0008fc e2811001 ADD r1,r1,#1
;;;515 Length--;
000900 e2422001 SUB r2,r2,#1
|L1.2308|
000904 e3520000 CMP r2,#0 ;508
000908 1afffff0 BNE |L1.2256|
00090c ea000011 B |L1.2392|
|L1.2320|
;;;516 }
;;;517
;;;518 }
;;;519 else if(portNum==3)
000910 e3500003 CMP r0,#3
000914 1a00000f BNE |L1.2392|
;;;520 {
;;;521 while ( Length != 0 )
000918 ea00000c B |L1.2384|
|L1.2332|
;;;522 {
;;;523 /* THRE status, contain valid data */
;;;524 while ( !(UART3TxEmpty & 0x01) );
00091c e1a00000 MOV r0,r0
|L1.2336|
000920 e59f3084 LDR r3,|L1.2476|
000924 e5d33000 LDRB r3,[r3,#0] ; UART3TxEmpty
000928 e3130001 TST r3,#1
00092c 0afffffb BEQ |L1.2336|
;;;525 U3THR = *BufferPtr;
000930 e5d13000 LDRB r3,[r1,#0]
000934 e59fc060 LDR r12,|L1.2460|
000938 e58c3000 STR r3,[r12,#0]
;;;526 UART3TxEmpty = 0; /* not empty in the THR until it shifts out */
00093c e3a03000 MOV r3,#0
000940 e59fc064 LDR r12,|L1.2476|
000944 e5cc3000 STRB r3,[r12,#0] ; UART3TxEmpty
;;;527 BufferPtr++;
000948 e2811001 ADD r1,r1,#1
;;;528 Length--;
00094c e2422001 SUB r2,r2,#1
|L1.2384|
000950 e3520000 CMP r2,#0 ;521
000954 1afffff0 BNE |L1.2332|
|L1.2392|
;;;529 }
;;;530 }
;;;531
;;;532 return;
;;;533 }
000958 e12fff1e BX lr
;;;534
ENDP
|L1.2396|
00095c e000c000 DCD 0xe000c000
|L1.2400|
000960 00000000 DCD UART0Status
|L1.2404|
000964 00000014 DCD ||.data||+0x14
|L1.2408|
000968 00000000 DCD UART0Buffer
|L1.2412|
00096c 00000000 DCD UART0Count
|L1.2416|
000970 00000000 DCD UART0TxEmpty
|L1.2420|
000974 e0010000 DCD 0xe0010000
|L1.2424|
000978 00000000 DCD UART1Status
|L1.2428|
00097c 00000000 DCD UART1Buffer
|L1.2432|
000980 00000000 DCD UART1Count
|L1.2436|
000984 00000000 DCD UART1TxEmpty
|L1.2440|
000988 e0078000 DCD 0xe0078000
|L1.2444|
00098c 00000000 DCD UART2Status
|L1.2448|
000990 00000000 DCD UART2Buffer
|L1.2452|
000994 00000000 DCD UART2Count
|L1.2456|
000998 00000000 DCD UART2TxEmpty
|L1.2460|
00099c e007c000 DCD 0xe007c000
|L1.2464|
0009a0 00000000 DCD UART3Status
|L1.2468|
0009a4 00000000 DCD UART3Buffer
|L1.2472|
0009a8 00000000 DCD UART3Count
|L1.2476|
0009ac 00000000 DCD UART3TxEmpty
|L1.2480|
0009b0 e002c000 DCD 0xe002c000
|L1.2484|
0009b4 001b7740 DCD 0x001b7740
|L1.2488|
0009b8 00000000 DCD UART0Handler
|L1.2492|
0009bc 00000000 DCD UART1Handler
|L1.2496|
0009c0 00000000 DCD UART2Handler
AREA ||.data||, DATA, ALIGN=2
UART0TxEmpty
000000 01 DCB 0x01
UART1TxEmpty
000001 01 DCB 0x01
UART2TxEmpty
000002 01 DCB 0x01
UART3TxEmpty
000003 01 DCB 0x01
UART0Count
000004 00000000 DCD 0x00000000
UART1Count
000008 00000000 DCD 0x00000000
UART2Count
00000c 00000000 DCD 0x00000000
UART3Count
000010 00000000 DCD 0x00000000
sysreg
000014 00000000 DCD 0x00000000
UART0Status
000018 00000000 DCD 0x00000000
UART1Status
00001c 00000000 DCD 0x00000000
UART2Status
000020 00000000 DCD 0x00000000
UART3Status
000024 00000000 DCD 0x00000000
AREA ||.bss||, DATA, NOINIT, ALIGN=0
UART0Buffer
% 64
UART1Buffer
% 64
UART2Buffer
% 64
UART3Buffer
% 64
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