📄 uart.txt
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000238 e59f3734 LDR r3,|L1.2420|
00023c e5933000 LDR r3,[r3,#0] ;151
000240 e59fc734 LDR r12,|L1.2428|
000244 e59fe734 LDR lr,|L1.2432|
000248 e59ee000 LDR lr,[lr,#0] ;151 ; UART1Count
00024c e7cc300e STRB r3,[r12,lr] ;151
000250 e59f3728 LDR r3,|L1.2432|
000254 e5933000 LDR r3,[r3,#0] ;152 ; UART1Count
000258 e2833001 ADD r3,r3,#1 ;152
00025c e59fc71c LDR r12,|L1.2432|
000260 e58c3000 STR r3,[r12,#0] ;152 ; UART1Count
000264 e28c3000 ADD r3,r12,#0 ;153
000268 e5933000 LDR r3,[r3,#0] ;153 ; UART1Count
00026c e3530040 CMP r3,#0x40 ;153
000270 1a000019 BNE |L1.732|
000274 e3a03000 MOV r3,#0 ;155
000278 e59fc700 LDR r12,|L1.2432|
00027c e58c3000 STR r3,[r12,#0] ;155 ; UART1Count
000280 ea000015 B |L1.732|
|L1.644|
000284 e3500006 CMP r0,#6 ;158
000288 1a000005 BNE |L1.676|
00028c e59f36e4 LDR r3,|L1.2424|
000290 e5933000 LDR r3,[r3,#0] ;161 ; UART1Status
000294 e3833c01 ORR r3,r3,#0x100 ;161
000298 e59fc6d8 LDR r12,|L1.2424|
00029c e58c3000 STR r3,[r12,#0] ;161 ; UART1Status
0002a0 ea00000d B |L1.732|
|L1.676|
0002a4 e3500001 CMP r0,#1 ;163
0002a8 1a00000b BNE |L1.732|
0002ac e59f36c0 LDR r3,|L1.2420|
0002b0 e5933014 LDR r3,[r3,#0x14] ;166
0002b4 e20310ff AND r1,r3,#0xff ;166
0002b8 e3110020 TST r1,#0x20 ;168
0002bc 0a000003 BEQ |L1.720|
0002c0 e3a03001 MOV r3,#1 ;170
0002c4 e59fc6b8 LDR r12,|L1.2436|
0002c8 e5cc3000 STRB r3,[r12,#0] ;170 ; UART1TxEmpty
0002cc ea000002 B |L1.732|
|L1.720|
0002d0 e3a03000 MOV r3,#0 ;174
0002d4 e59fc6a8 LDR r12,|L1.2436|
0002d8 e5cc3000 STRB r3,[r12,#0] ;174 ; UART1TxEmpty
|L1.732|
0002dc e3a03000 MOV r3,#0 ;179
0002e0 e5033100 STR r3,[r3,#-0x100] ;179
0002e4 eaffffba B |L1.468|
;;;181
ENDP
UART2Handler PROC
;;;193 void UART2Handler (void) __irq
;;;194 {
0002e8 e92d500f PUSH {r0-r3,r12,lr}
;;;195
;;;196 BYTE IIRValue, LSRValue;
;;;197 BYTE Dummy = Dummy;
0002ec e1a00000 MOV r0,r0
;;;198
;;;199 // IENABLE; /* handles nested interrupt */
;;;200 IIRValue = U2IIR;
0002f0 e59f3690 LDR r3,|L1.2440|
0002f4 e5930008 LDR r0,[r3,#8]
;;;201
;;;202 IIRValue >>= 1; /* skip pending bit in IIR */
0002f8 e1a000c0 ASR r0,r0,#1
;;;203 IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
0002fc e2000007 AND r0,r0,#7
;;;204 if ( IIRValue == IIR_RLS ) /* Receive Line Status */
000300 e3500003 CMP r0,#3
000304 1a000026 BNE |L1.932|
;;;205 {
;;;206 LSRValue = U2LSR;
000308 e59f3678 LDR r3,|L1.2440|
00030c e5933014 LDR r3,[r3,#0x14]
000310 e20310ff AND r1,r3,#0xff
;;;207 /* Receive Line Status */
;;;208 if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
000314 e311009e TST r1,#0x9e
000318 0a00000c BEQ |L1.848|
;;;209 {
;;;210 /* There are errors or break interrupt */
;;;211 /* Read LSR will clear the interrupt */
;;;212 UART2Status = LSRValue;
00031c e59f3668 LDR r3,|L1.2444|
000320 e5831000 STR r1,[r3,#0] ; UART2Status
;;;213 Dummy = U2RBR; /* Dummy read on RX to clear
000324 e59f365c LDR r3,|L1.2440|
000328 e5933000 LDR r3,[r3,#0]
00032c e20320ff AND r2,r3,#0xff
;;;214 interrupt, then bail out */
;;;215 IDISABLE;
000330 e321f092 MSR CPSR_c,#0x92
000334 e59f3628 LDR r3,|L1.2404|
000338 e5933000 LDR r3,[r3,#0] ; sysreg
00033c e16ff003 MSR SPSR_cxsf,r3
;;;216 VICVectAddr = 0; /* Acknowledge Interrupt */
000340 e3a03000 MOV r3,#0
000344 e5033100 STR r3,[r3,#-0x100]
|L1.840|
;;;217 return;
;;;218 }
;;;219 if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
;;;220 {
;;;221 /* If no error on RLS, normal ready, save into the data buffer. */
;;;222 /* Note: read RBR will clear the interrupt */
;;;223 UART2Buffer[UART0Count] = U0RBR;
;;;224 UART2Count++;
;;;225 if ( UART2Count == BUFSIZE )
;;;226 {
;;;227 UART2Count = 0; /* buffer overflow */
;;;228 }
;;;229 }
;;;230 }
;;;231 else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
;;;232 {
;;;233 /* Receive Data Available */
;;;234 UART2Buffer[UART2Count] = U2RBR;
;;;235 UART2Count++;
;;;236 if ( UART2Count == BUFSIZE )
;;;237 {
;;;238 UART2Count = 0; /* buffer overflow */
;;;239 }
;;;240 }
;;;241 else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
;;;242 {
;;;243 /* Character Time-out indicator */
;;;244 UART2Status |= 0x100; /* Bit 9 as the CTI error */
;;;245 }
;;;246 else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
;;;247 {
;;;248 /* THRE interrupt */
;;;249 LSRValue = U2LSR; /* Check status in the LSR to see if
;;;250 valid data in U0THR or not */
;;;251 if ( LSRValue & LSR_THRE )
;;;252 {
;;;253 UART2TxEmpty = 1;
;;;254 }
;;;255 else
;;;256 {
;;;257 UART2TxEmpty = 0;
;;;258 }
;;;259 }
;;;260
;;;261 // IDISABLE;
;;;262 VICVectAddr = 0; /* Acknowledge Interrupt */
;;;263
;;;264
;;;265 }
000348 e8bd500f POP {r0-r3,r12,lr}
00034c e25ef004 SUBS pc,lr,#4
|L1.848|
000350 e3110001 TST r1,#1 ;219
000354 0a00003d BEQ |L1.1104|
000358 e59f35fc LDR r3,|L1.2396|
00035c e5933000 LDR r3,[r3,#0] ;223
000360 e59fc628 LDR r12,|L1.2448|
000364 e59fe600 LDR lr,|L1.2412|
000368 e59ee000 LDR lr,[lr,#0] ;223 ; UART0Count
00036c e7cc300e STRB r3,[r12,lr] ;223
000370 e59f361c LDR r3,|L1.2452|
000374 e5933000 LDR r3,[r3,#0] ;224 ; UART2Count
000378 e2833001 ADD r3,r3,#1 ;224
00037c e59fc610 LDR r12,|L1.2452|
000380 e58c3000 STR r3,[r12,#0] ;224 ; UART2Count
000384 e28c3000 ADD r3,r12,#0 ;225
000388 e5933000 LDR r3,[r3,#0] ;225 ; UART2Count
00038c e3530040 CMP r3,#0x40 ;225
000390 1a00002e BNE |L1.1104|
000394 e3a03000 MOV r3,#0 ;227
000398 e59fc5f4 LDR r12,|L1.2452|
00039c e58c3000 STR r3,[r12,#0] ;227 ; UART2Count
0003a0 ea00002a B |L1.1104|
|L1.932|
0003a4 e3500002 CMP r0,#2 ;231
0003a8 1a000012 BNE |L1.1016|
0003ac e59f35d4 LDR r3,|L1.2440|
0003b0 e5933000 LDR r3,[r3,#0] ;234
0003b4 e59fc5d4 LDR r12,|L1.2448|
0003b8 e59fe5d4 LDR lr,|L1.2452|
0003bc e59ee000 LDR lr,[lr,#0] ;234 ; UART2Count
0003c0 e7cc300e STRB r3,[r12,lr] ;234
0003c4 e59f35c8 LDR r3,|L1.2452|
0003c8 e5933000 LDR r3,[r3,#0] ;235 ; UART2Count
0003cc e2833001 ADD r3,r3,#1 ;235
0003d0 e59fc5bc LDR r12,|L1.2452|
0003d4 e58c3000 STR r3,[r12,#0] ;235 ; UART2Count
0003d8 e28c3000 ADD r3,r12,#0 ;236
0003dc e5933000 LDR r3,[r3,#0] ;236 ; UART2Count
0003e0 e3530040 CMP r3,#0x40 ;236
0003e4 1a000019 BNE |L1.1104|
0003e8 e3a03000 MOV r3,#0 ;238
0003ec e59fc5a0 LDR r12,|L1.2452|
0003f0 e58c3000 STR r3,[r12,#0] ;238 ; UART2Count
0003f4 ea000015 B |L1.1104|
|L1.1016|
0003f8 e3500006 CMP r0,#6 ;241
0003fc 1a000005 BNE |L1.1048|
000400 e59f3584 LDR r3,|L1.2444|
000404 e5933000 LDR r3,[r3,#0] ;244 ; UART2Status
000408 e3833c01 ORR r3,r3,#0x100 ;244
00040c e59fc578 LDR r12,|L1.2444|
000410 e58c3000 STR r3,[r12,#0] ;244 ; UART2Status
000414 ea00000d B |L1.1104|
|L1.1048|
000418 e3500001 CMP r0,#1 ;246
00041c 1a00000b BNE |L1.1104|
000420 e59f3560 LDR r3,|L1.2440|
000424 e5933014 LDR r3,[r3,#0x14] ;249
000428 e20310ff AND r1,r3,#0xff ;249
00042c e3110020 TST r1,#0x20 ;251
000430 0a000003 BEQ |L1.1092|
000434 e3a03001 MOV r3,#1 ;253
000438 e59fc558 LDR r12,|L1.2456|
00043c e5cc3000 STRB r3,[r12,#0] ;253 ; UART2TxEmpty
000440 ea000002 B |L1.1104|
|L1.1092|
000444 e3a03000 MOV r3,#0 ;257
000448 e59fc548 LDR r12,|L1.2456|
00044c e5cc3000 STRB r3,[r12,#0] ;257 ; UART2TxEmpty
|L1.1104|
000450 e3a03000 MOV r3,#0 ;262
000454 e5033100 STR r3,[r3,#-0x100] ;262
000458 eaffffba B |L1.840|
;;;266
ENDP
UART3Handler PROC
;;;280 void UART3Handler (void) __irq
;;;281 {
00045c e92d500f PUSH {r0-r3,r12,lr}
;;;282
;;;283 BYTE IIRValue, LSRValue;
;;;284 BYTE Dummy = Dummy;
000460 e1a00000 MOV r0,r0
;;;285
;;;286 // IENABLE; /* handles nested interrupt */
;;;287 IIRValue = U3IIR;
000464 e59f3530 LDR r3,|L1.2460|
000468 e5930008 LDR r0,[r3,#8]
;;;288
;;;289 IIRValue >>= 1; /* skip pending bit in IIR */
00046c e1a000c0 ASR r0,r0,#1
;;;290 IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
000470 e2000007 AND r0,r0,#7
;;;291 if ( IIRValue == IIR_RLS ) /* Receive Line Status */
000474 e3500003 CMP r0,#3
000478 1a000026 BNE |L1.1304|
;;;292 {
;;;293 LSRValue = U3LSR;
00047c e59f3518 LDR r3,|L1.2460|
000480 e5933014 LDR r3,[r3,#0x14]
000484 e20310ff AND r1,r3,#0xff
;;;294 /* Receive Line Status */
;;;295 if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
000488 e311009e TST r1,#0x9e
00048c 0a00000c BEQ |L1.1220|
;;;296 {
;;;297 /* There are errors or break interrupt */
;;;298 /* Read LSR will clear the interrupt */
;;;299 UART3Status = LSRValue;
000490 e59f3508 LDR r3,|L1.2464|
000494 e5831000 STR r1,[r3,#0] ; UART3Status
;;;300 Dummy = U3RBR; /* Dummy read on RX to clear
000498 e59f34fc LDR r3,|L1.2460|
00049c e5933000 LDR r3,[r3,#0]
0004a0 e20320ff AND r2,r3,#0xff
;;;301 interrupt, then bail out */
;;;302 IDISABLE;
0004a4 e321f092 MSR CPSR_c,#0x92
0004a8 e59f34b4 LDR r3,|L1.2404|
0004ac e5933000 LDR r3,[r3,#0] ; sysreg
0004b0 e16ff003 MSR SPSR_cxsf,r3
;;;303 VICVectAddr = 0; /* Acknowledge Interrupt */
0004b4 e3a03000 MOV r3,#0
0004b8 e5033100 STR r3,[r3,#-0x100]
|L1.1212|
;;;304 return;
;;;305 }
;;;306 if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
;;;307 {
;;;308 /* If no error on RLS, normal ready, save into the data buffer. */
;;;309 /* Note: read RBR will clear the interrupt */
;;;310 UART3Buffer[UART3Count] = U0RBR;
;;;311 UART3Count++;
;;;312 if ( UART3Count == BUFSIZE )
;;;313 {
;;;314 UART3Count = 0; /* buffer overflow */
;;;315 }
;;;316 }
;;;317 }
;;;318 else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
;;;319 {
;;;320 /* Receive Data Available */
;;;321 UART3Buffer[UART3Count] = U3RBR;
;;;322 UART3Count++;
;;;323 if ( UART3Count == BUFSIZE )
;;;324 {
;;;325 UART3Count = 0; /* buffer overflow */
;;;326 }
;;;327 }
;;;328 else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
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