📄 uart.txt
字号:
; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 939] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\obj\uart.o --depend=.\obj\uart.d --device=DARMP --apcs=interwork -O0 -IC:\Keil\ARM\INC\Philips --omf_browse=.\obj\uart.crf uart.c]
ARM
AREA ||.text||, CODE, READONLY, ALIGN=2
UART0Handler PROC
;;;31 void UART0Handler (void) __irq
;;;32 {
000000 e92d500f PUSH {r0-r3,r12,lr}
;;;33 BYTE IIRValue, LSRValue;
;;;34 BYTE Dummy = Dummy;
000004 e1a00000 MOV r0,r0
;;;35
;;;36 // IENABLE; /* handles nested interrupt */
;;;37 IIRValue = U0IIR;
000008 e59f394c LDR r3,|L1.2396|
00000c e5930008 LDR r0,[r3,#8]
;;;38
;;;39 IIRValue >>= 1; /* skip pending bit in IIR */
000010 e1a000c0 ASR r0,r0,#1
;;;40 IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
000014 e2000007 AND r0,r0,#7
;;;41 if ( IIRValue == IIR_RLS ) /* Receive Line Status */
000018 e3500003 CMP r0,#3
00001c 1a000026 BNE |L1.188|
;;;42 {
;;;43 LSRValue = U0LSR;
000020 e59f3934 LDR r3,|L1.2396|
000024 e5933014 LDR r3,[r3,#0x14]
000028 e20310ff AND r1,r3,#0xff
;;;44 /* Receive Line Status */
;;;45 if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
00002c e311009e TST r1,#0x9e
000030 0a00000c BEQ |L1.104|
;;;46 {
;;;47 /* There are errors or break interrupt */
;;;48 /* Read LSR will clear the interrupt */
;;;49 UART0Status = LSRValue;
000034 e59f3924 LDR r3,|L1.2400|
000038 e5831000 STR r1,[r3,#0] ; UART0Status
;;;50 Dummy = U0RBR; /* Dummy read on RX to clear
00003c e59f3918 LDR r3,|L1.2396|
000040 e5933000 LDR r3,[r3,#0]
000044 e20320ff AND r2,r3,#0xff
;;;51 interrupt, then bail out */
;;;52 IDISABLE;
000048 e321f092 MSR CPSR_c,#0x92
00004c e59f3910 LDR r3,|L1.2404|
000050 e5933000 LDR r3,[r3,#0] ; sysreg
000054 e16ff003 MSR SPSR_cxsf,r3
;;;53 VICVectAddr = 0; /* Acknowledge Interrupt */
000058 e3a03000 MOV r3,#0
00005c e5033100 STR r3,[r3,#-0x100]
|L1.96|
;;;54 return;
;;;55 }
;;;56 if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
;;;57 {
;;;58 /* If no error on RLS, normal ready, save into the data buffer. */
;;;59 /* Note: read RBR will clear the interrupt */
;;;60 UART0Buffer[UART0Count] = U0RBR;
;;;61 UART0Count++;
;;;62 if ( UART0Count == BUFSIZE )
;;;63 {
;;;64 UART0Count = 0; /* buffer overflow */
;;;65 }
;;;66 }
;;;67 }
;;;68 else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
;;;69 {
;;;70 /* Receive Data Available */
;;;71 UART0Buffer[UART0Count] = U0RBR;
;;;72 UART0Count++;
;;;73 if ( UART0Count == BUFSIZE )
;;;74 {
;;;75 UART0Count = 0; /* buffer overflow */
;;;76 }
;;;77 }
;;;78 else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
;;;79 {
;;;80 /* Character Time-out indicator */
;;;81 UART0Status |= 0x100; /* Bit 9 as the CTI error */
;;;82 }
;;;83 else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
;;;84 {
;;;85 /* THRE interrupt */
;;;86 LSRValue = U0LSR; /* Check status in the LSR to see if
;;;87 valid data in U0THR or not */
;;;88 if ( LSRValue & LSR_THRE )
;;;89 {
;;;90 UART0TxEmpty = 1;
;;;91 }
;;;92 else
;;;93 {
;;;94 UART0TxEmpty = 0;
;;;95 }
;;;96 }
;;;97
;;;98 // IDISABLE;
;;;99 VICVectAddr = 0; /* Acknowledge Interrupt */
;;;100 }
000060 e8bd500f POP {r0-r3,r12,lr}
000064 e25ef004 SUBS pc,lr,#4
|L1.104|
000068 e3110001 TST r1,#1 ;56
00006c 0a00003d BEQ |L1.360|
000070 e59f38e4 LDR r3,|L1.2396|
000074 e5933000 LDR r3,[r3,#0] ;60
000078 e59fc8e8 LDR r12,|L1.2408|
00007c e59fe8e8 LDR lr,|L1.2412|
000080 e59ee000 LDR lr,[lr,#0] ;60 ; UART0Count
000084 e7cc300e STRB r3,[r12,lr] ;60
000088 e59f38dc LDR r3,|L1.2412|
00008c e5933000 LDR r3,[r3,#0] ;61 ; UART0Count
000090 e2833001 ADD r3,r3,#1 ;61
000094 e59fc8d0 LDR r12,|L1.2412|
000098 e58c3000 STR r3,[r12,#0] ;61 ; UART0Count
00009c e28c3000 ADD r3,r12,#0 ;62
0000a0 e5933000 LDR r3,[r3,#0] ;62 ; UART0Count
0000a4 e3530040 CMP r3,#0x40 ;62
0000a8 1a00002e BNE |L1.360|
0000ac e3a03000 MOV r3,#0 ;64
0000b0 e59fc8b4 LDR r12,|L1.2412|
0000b4 e58c3000 STR r3,[r12,#0] ;64 ; UART0Count
0000b8 ea00002a B |L1.360|
|L1.188|
0000bc e3500002 CMP r0,#2 ;68
0000c0 1a000012 BNE |L1.272|
0000c4 e59f3890 LDR r3,|L1.2396|
0000c8 e5933000 LDR r3,[r3,#0] ;71
0000cc e59fc894 LDR r12,|L1.2408|
0000d0 e59fe894 LDR lr,|L1.2412|
0000d4 e59ee000 LDR lr,[lr,#0] ;71 ; UART0Count
0000d8 e7cc300e STRB r3,[r12,lr] ;71
0000dc e59f3888 LDR r3,|L1.2412|
0000e0 e5933000 LDR r3,[r3,#0] ;72 ; UART0Count
0000e4 e2833001 ADD r3,r3,#1 ;72
0000e8 e59fc87c LDR r12,|L1.2412|
0000ec e58c3000 STR r3,[r12,#0] ;72 ; UART0Count
0000f0 e28c3000 ADD r3,r12,#0 ;73
0000f4 e5933000 LDR r3,[r3,#0] ;73 ; UART0Count
0000f8 e3530040 CMP r3,#0x40 ;73
0000fc 1a000019 BNE |L1.360|
000100 e3a03000 MOV r3,#0 ;75
000104 e59fc860 LDR r12,|L1.2412|
000108 e58c3000 STR r3,[r12,#0] ;75 ; UART0Count
00010c ea000015 B |L1.360|
|L1.272|
000110 e3500006 CMP r0,#6 ;78
000114 1a000005 BNE |L1.304|
000118 e59f3840 LDR r3,|L1.2400|
00011c e5933000 LDR r3,[r3,#0] ;81 ; UART0Status
000120 e3833c01 ORR r3,r3,#0x100 ;81
000124 e59fc834 LDR r12,|L1.2400|
000128 e58c3000 STR r3,[r12,#0] ;81 ; UART0Status
00012c ea00000d B |L1.360|
|L1.304|
000130 e3500001 CMP r0,#1 ;83
000134 1a00000b BNE |L1.360|
000138 e59f381c LDR r3,|L1.2396|
00013c e5933014 LDR r3,[r3,#0x14] ;86
000140 e20310ff AND r1,r3,#0xff ;86
000144 e3110020 TST r1,#0x20 ;88
000148 0a000003 BEQ |L1.348|
00014c e3a03001 MOV r3,#1 ;90
000150 e59fc818 LDR r12,|L1.2416|
000154 e5cc3000 STRB r3,[r12,#0] ;90 ; UART0TxEmpty
000158 ea000002 B |L1.360|
|L1.348|
00015c e3a03000 MOV r3,#0 ;94
000160 e59fc808 LDR r12,|L1.2416|
000164 e5cc3000 STRB r3,[r12,#0] ;94 ; UART0TxEmpty
|L1.360|
000168 e3a03000 MOV r3,#0 ;99
00016c e5033100 STR r3,[r3,#-0x100] ;99
000170 eaffffba B |L1.96|
;;;101
ENDP
UART1Handler PROC
;;;111 void UART1Handler (void) __irq
;;;112 {
000174 e92d500f PUSH {r0-r3,r12,lr}
;;;113 BYTE IIRValue, LSRValue;
;;;114 BYTE Dummy = Dummy;
000178 e1a00000 MOV r0,r0
;;;115
;;;116 // IENABLE; /* handles nested interrupt */
;;;117 IIRValue = U1IIR;
00017c e59f37f0 LDR r3,|L1.2420|
000180 e5930008 LDR r0,[r3,#8]
;;;118
;;;119 IIRValue >>= 1; /* skip pending bit in IIR */
000184 e1a000c0 ASR r0,r0,#1
;;;120 IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
000188 e2000007 AND r0,r0,#7
;;;121 if ( IIRValue == IIR_RLS ) /* Receive Line Status */
00018c e3500003 CMP r0,#3
000190 1a000026 BNE |L1.560|
;;;122 {
;;;123 LSRValue = U1LSR;
000194 e59f37d8 LDR r3,|L1.2420|
000198 e5933014 LDR r3,[r3,#0x14]
00019c e20310ff AND r1,r3,#0xff
;;;124 /* Receive Line Status */
;;;125 if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
0001a0 e311009e TST r1,#0x9e
0001a4 0a00000c BEQ |L1.476|
;;;126 {
;;;127 /* There are errors or break interrupt */
;;;128 /* Read LSR will clear the interrupt */
;;;129 UART1Status = LSRValue;
0001a8 e59f37c8 LDR r3,|L1.2424|
0001ac e5831000 STR r1,[r3,#0] ; UART1Status
;;;130 Dummy = U1RBR; /* Dummy read on RX to clear
0001b0 e59f37bc LDR r3,|L1.2420|
0001b4 e5933000 LDR r3,[r3,#0]
0001b8 e20320ff AND r2,r3,#0xff
;;;131 interrupt, then bail out */
;;;132 IDISABLE;
0001bc e321f092 MSR CPSR_c,#0x92
0001c0 e59f379c LDR r3,|L1.2404|
0001c4 e5933000 LDR r3,[r3,#0] ; sysreg
0001c8 e16ff003 MSR SPSR_cxsf,r3
;;;133 VICVectAddr = 0; /* Acknowledge Interrupt */
0001cc e3a03000 MOV r3,#0
0001d0 e5033100 STR r3,[r3,#-0x100]
|L1.468|
;;;134 return;
;;;135 }
;;;136 if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
;;;137 {
;;;138 /* If no error on RLS, normal ready, save into the data buffer. */
;;;139 /* Note: read RBR will clear the interrupt */
;;;140 UART1Buffer[UART1Count] = U1RBR;
;;;141 UART1Count++;
;;;142 if ( UART1Count == BUFSIZE )
;;;143 {
;;;144 UART1Count = 0; /* buffer overflow */
;;;145 }
;;;146 }
;;;147 }
;;;148 else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
;;;149 {
;;;150 /* Receive Data Available */
;;;151 UART1Buffer[UART1Count] = U1RBR;
;;;152 UART1Count++;
;;;153 if ( UART1Count == BUFSIZE )
;;;154 {
;;;155 UART1Count = 0; /* buffer overflow */
;;;156 }
;;;157 }
;;;158 else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
;;;159 {
;;;160 /* Character Time-out indicator */
;;;161 UART1Status |= 0x100; /* Bit 9 as the CTI error */
;;;162 }
;;;163 else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
;;;164 {
;;;165 /* THRE interrupt */
;;;166 LSRValue = U1LSR; /* Check status in the LSR to see if
;;;167 valid data in U0THR or not */
;;;168 if ( LSRValue & LSR_THRE )
;;;169 {
;;;170 UART1TxEmpty = 1;
;;;171 }
;;;172 else
;;;173 {
;;;174 UART1TxEmpty = 0;
;;;175 }
;;;176 }
;;;177
;;;178 // IDISABLE;
;;;179 VICVectAddr = 0; /* Acknowledge Interrupt */
;;;180 }
0001d4 e8bd500f POP {r0-r3,r12,lr}
0001d8 e25ef004 SUBS pc,lr,#4
|L1.476|
0001dc e3110001 TST r1,#1 ;136
0001e0 0a00003d BEQ |L1.732|
0001e4 e59f3788 LDR r3,|L1.2420|
0001e8 e5933000 LDR r3,[r3,#0] ;140
0001ec e59fc788 LDR r12,|L1.2428|
0001f0 e59fe788 LDR lr,|L1.2432|
0001f4 e59ee000 LDR lr,[lr,#0] ;140 ; UART1Count
0001f8 e7cc300e STRB r3,[r12,lr] ;140
0001fc e59f377c LDR r3,|L1.2432|
000200 e5933000 LDR r3,[r3,#0] ;141 ; UART1Count
000204 e2833001 ADD r3,r3,#1 ;141
000208 e59fc770 LDR r12,|L1.2432|
00020c e58c3000 STR r3,[r12,#0] ;141 ; UART1Count
000210 e28c3000 ADD r3,r12,#0 ;142
000214 e5933000 LDR r3,[r3,#0] ;142 ; UART1Count
000218 e3530040 CMP r3,#0x40 ;142
00021c 1a00002e BNE |L1.732|
000220 e3a03000 MOV r3,#0 ;144
000224 e59fc754 LDR r12,|L1.2432|
000228 e58c3000 STR r3,[r12,#0] ;144 ; UART1Count
00022c ea00002a B |L1.732|
|L1.560|
000230 e3500002 CMP r0,#2 ;148
000234 1a000012 BNE |L1.644|
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -