📄 target.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 939] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\obj\target.o --depend=.\obj\target.d --device=DARMP --apcs=interwork -O0 -IC:\Keil\ARM\INC\Philips --omf_browse=.\obj\target.crf target.c]
ARM
AREA ||.text||, CODE, READONLY, ALIGN=2
TargetInit PROC
;;;29 return;
;;;30 }
000000 e12fff1e BX lr
;;;31
ENDP
GPIOResetInit PROC
;;;45 /* Reset all GPIO pins to default: primary function */
;;;46 PINSEL0 = 0x00000000;
000004 e3a00000 MOV r0,#0
000008 e59f1208 LDR r1,|L1.536|
00000c e5810000 STR r0,[r1,#0]
;;;47 PINSEL1 = 0x00000000;
000010 e5810004 STR r0,[r1,#4]
;;;48 PINSEL2 = 0x00000000;
000014 e5810008 STR r0,[r1,#8]
;;;49 PINSEL3 = 0x00000000;
000018 e581000c STR r0,[r1,#0xc]
;;;50 PINSEL4 = 0x00000000;
00001c e5810010 STR r0,[r1,#0x10]
;;;51 PINSEL5 = 0x00000000;
000020 e5810014 STR r0,[r1,#0x14]
;;;52 PINSEL6 = 0x00000000;
000024 e5810018 STR r0,[r1,#0x18]
;;;53 PINSEL7 = 0x00000000;
000028 e581001c STR r0,[r1,#0x1c]
;;;54 PINSEL8 = 0x00000000;
00002c e5810020 STR r0,[r1,#0x20]
;;;55 PINSEL9 = 0x00000000;
000030 e5810024 STR r0,[r1,#0x24]
;;;56 PINSEL10 = 0x00000000;
000034 e5810028 STR r0,[r1,#0x28]
;;;57
;;;58 IODIR0 = 0x00000000;
000038 e2411901 SUB r1,r1,#0x4000
00003c e5810008 STR r0,[r1,#8]
;;;59 IODIR1 = 0x00000000;
000040 e5810018 STR r0,[r1,#0x18]
;;;60 IOSET0 = 0x00000000;
000044 e5810004 STR r0,[r1,#4]
;;;61 IOSET1 = 0x00000000;
000048 e5810014 STR r0,[r1,#0x14]
;;;62
;;;63 FIO0DIR = 0x00000000;
00004c e59f11c8 LDR r1,|L1.540|
000050 e5810000 STR r0,[r1,#0]
;;;64 FIO1DIR = 0x00000000;
000054 e5810020 STR r0,[r1,#0x20]
;;;65 FIO2DIR = 0x00000000;
000058 e5810040 STR r0,[r1,#0x40]
;;;66 FIO3DIR = 0x00000000;
00005c e5810060 STR r0,[r1,#0x60]
;;;67 FIO4DIR = 0x00000000;
000060 e5810080 STR r0,[r1,#0x80]
;;;68
;;;69 FIO0SET = 0x00000000;
000064 e5810018 STR r0,[r1,#0x18]
;;;70 FIO1SET = 0x00000000;
000068 e5810038 STR r0,[r1,#0x38]
;;;71 FIO2SET = 0x00000000;
00006c e5810058 STR r0,[r1,#0x58]
;;;72 FIO3SET = 0x00000000;
000070 e5810078 STR r0,[r1,#0x78]
;;;73 FIO4SET = 0x00000000;
000074 e5810098 STR r0,[r1,#0x98]
;;;74
;;;75 FIO0MASK=0X00000000;
000078 e5810010 STR r0,[r1,#0x10]
;;;76 FIO1MASK=0X00000000;
00007c e5810030 STR r0,[r1,#0x30]
;;;77 FIO2MASK=0X00000000;
000080 e5810050 STR r0,[r1,#0x50]
;;;78 FIO3MASK=0X00000000;
000084 e5810070 STR r0,[r1,#0x70]
;;;79 FIO4MASK=0X00000000;
000088 e5810090 STR r0,[r1,#0x90]
;;;80
;;;81 return;
;;;82 }
00008c e12fff1e BX lr
;;;83
ENDP
ConfigurePLL PROC
;;;100
;;;101 if ( PLLSTAT & (1 << 25) )
000090 e59f2188 LDR r2,|L1.544|
000094 e5922088 LDR r2,[r2,#0x88]
000098 e3120402 TST r2,#0x2000000
00009c 0a000006 BEQ |L1.188|
;;;102 {
;;;103 PLLCON = 1; /* Enable PLL, disconnected */
0000a0 e3a02001 MOV r2,#1
0000a4 e59f3174 LDR r3,|L1.544|
0000a8 e5832080 STR r2,[r3,#0x80]
;;;104 PLLFEED = 0xaa;
0000ac e3a020aa MOV r2,#0xaa
0000b0 e583208c STR r2,[r3,#0x8c]
;;;105 PLLFEED = 0x55;
0000b4 e3a02055 MOV r2,#0x55
0000b8 e583208c STR r2,[r3,#0x8c]
|L1.188|
;;;106 }
;;;107
;;;108 PLLCON = 0; /* Disable PLL, disconnected */
0000bc e3a02000 MOV r2,#0
0000c0 e59f3158 LDR r3,|L1.544|
0000c4 e5832080 STR r2,[r3,#0x80]
;;;109 PLLFEED = 0xaa;
0000c8 e3a020aa MOV r2,#0xaa
0000cc e583208c STR r2,[r3,#0x8c]
;;;110 PLLFEED = 0x55;
0000d0 e3a02055 MOV r2,#0x55
0000d4 e583208c STR r2,[r3,#0x8c]
;;;111
;;;112 SCS |= 0x20; /* Enable main OSC */
0000d8 e1c32002 BIC r2,r3,r2
0000dc e59221a0 LDR r2,[r2,#0x1a0]
0000e0 e3822020 ORR r2,r2,#0x20
0000e4 e58321a0 STR r2,[r3,#0x1a0]
;;;113 while( !(SCS & 0x40) ); /* Wait until main OSC is usable */
0000e8 e1a00000 MOV r0,r0
|L1.236|
0000ec e59f212c LDR r2,|L1.544|
0000f0 e59221a0 LDR r2,[r2,#0x1a0]
0000f4 e3120040 TST r2,#0x40
0000f8 0afffffb BEQ |L1.236|
;;;114
;;;115 CLKSRCSEL = 0x1; /* select main OSC, 12MHz, as the PLL clock source */
0000fc e3a02001 MOV r2,#1
000100 e59f3118 LDR r3,|L1.544|
000104 e583210c STR r2,[r3,#0x10c]
;;;116
;;;117 PLLCFG = PLL_MValue | (PLL_NValue << 16);
000108 e3a0200b MOV r2,#0xb
00010c e5832084 STR r2,[r3,#0x84]
;;;118 PLLFEED = 0xaa;
000110 e3a020aa MOV r2,#0xaa
000114 e583208c STR r2,[r3,#0x8c]
;;;119 PLLFEED = 0x55;
000118 e3a02055 MOV r2,#0x55
00011c e583208c STR r2,[r3,#0x8c]
;;;120
;;;121 PLLCON = 1; /* Enable PLL, disconnected */
000120 e3a02001 MOV r2,#1
000124 e5832080 STR r2,[r3,#0x80]
;;;122 PLLFEED = 0xaa;
000128 e3a020aa MOV r2,#0xaa
00012c e583208c STR r2,[r3,#0x8c]
;;;123 PLLFEED = 0x55;
000130 e3a02055 MOV r2,#0x55
000134 e583208c STR r2,[r3,#0x8c]
;;;124
;;;125 CCLKCFG = CCLKDivValue; /* Set clock divider */
000138 e3a02004 MOV r2,#4
00013c e5832104 STR r2,[r3,#0x104]
;;;126 #if USE_USB
;;;127 USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
000140 e3a02005 MOV r2,#5
000144 e5832108 STR r2,[r3,#0x108]
;;;128 #endif
;;;129
;;;130 while ( ((PLLSTAT & (1 << 26)) == 0) ); /* Check lock bit status */
000148 e1a00000 MOV r0,r0
|L1.332|
00014c e59f20cc LDR r2,|L1.544|
000150 e5922088 LDR r2,[r2,#0x88]
000154 e3120301 TST r2,#0x4000000
000158 0afffffb BEQ |L1.332|
;;;131
;;;132 MValue = PLLSTAT & 0x00007FFF;
00015c e59f20bc LDR r2,|L1.544|
000160 e5922088 LDR r2,[r2,#0x88]
000164 e1a00882 LSL r0,r2,#17
000168 e1a008a0 LSR r0,r0,#17
;;;133 NValue = (PLLSTAT & 0x00FF0000) >> 16;
00016c e59f20ac LDR r2,|L1.544|
000170 e5922088 LDR r2,[r2,#0x88]
000174 e20228ff AND r2,r2,#0xff0000
000178 e1a01822 LSR r1,r2,#16
;;;134 while ((MValue != PLL_MValue) && ( NValue != PLL_NValue) );
00017c e1a00000 MOV r0,r0
|L1.384|
000180 e350000b CMP r0,#0xb
000184 0a000001 BEQ |L1.400|
000188 e3510000 CMP r1,#0
00018c 1afffffb BNE |L1.384|
|L1.400|
;;;135
;;;136 PLLCON = 3; /* enable and connect */
000190 e3a02003 MOV r2,#3
000194 e59f3084 LDR r3,|L1.544|
000198 e5832080 STR r2,[r3,#0x80]
;;;137 PLLFEED = 0xaa;
00019c e3a020aa MOV r2,#0xaa
0001a0 e583208c STR r2,[r3,#0x8c]
;;;138 PLLFEED = 0x55;
0001a4 e3a02055 MOV r2,#0x55
0001a8 e583208c STR r2,[r3,#0x8c]
;;;139 while ( ((PLLSTAT & (1 << 25)) == 0) ); /* Check connect bit status */
0001ac e1a00000 MOV r0,r0
|L1.432|
0001b0 e59f2068 LDR r2,|L1.544|
0001b4 e5922088 LDR r2,[r2,#0x88]
0001b8 e3120402 TST r2,#0x2000000
0001bc 0afffffb BEQ |L1.432|
;;;140 return;
;;;141 }
0001c0 e12fff1e BX lr
;;;142
ENDP
TargetResetInit PROC
;;;154 void TargetResetInit(void)
;;;155 {
0001c4 e92d4010 PUSH {r4,lr}
;;;156 #ifdef __DEBUG_RAM
;;;157 MEMMAP = 0x2; /* remap to internal RAM */
;;;158 #endif
;;;159
;;;160 #ifdef __DEBUG_FLASH
;;;161 MEMMAP = 0x1; /* remap to internal flash */
;;;162 #endif
;;;163
;;;164 #if USE_USB
;;;165 PCONP |= 0x80000000; /* Turn On USB PCLK */
0001c8 e59f0050 LDR r0,|L1.544|
0001cc e59000c4 LDR r0,[r0,#0xc4]
0001d0 e3800102 ORR r0,r0,#0x80000000
0001d4 e59f1044 LDR r1,|L1.544|
0001d8 e58100c4 STR r0,[r1,#0xc4]
;;;166 #endif
;;;167 /* Configure PLL, switch from IRC to Main OSC */
;;;168 ConfigurePLL();
0001dc ebfffffe BL ConfigurePLL
;;;169
;;;170 /* Set system timers for each component */
;;;171 #if (Fpclk / (Fcclk / 4)) == 1
;;;172 PCLKSEL0 = 0x00000000; /* PCLK is 1/4 CCLK */
;;;173 PCLKSEL1 = 0x00000000;
;;;174 #endif
;;;175 #if (Fpclk / (Fcclk / 4)) == 2
;;;176 PCLKSEL0 = 0xAAAAAAAA; /* PCLK is 1/2 CCLK */
0001e0 e59f003c LDR r0,|L1.548|
0001e4 e59f1034 LDR r1,|L1.544|
0001e8 e58101a8 STR r0,[r1,#0x1a8]
;;;177 PCLKSEL1 = 0xAAAAAAAA;
0001ec e58101ac STR r0,[r1,#0x1ac]
;;;178 #endif
;;;179 #if (Fpclk / (Fcclk / 4)) == 4
;;;180 PCLKSEL0 = 0x55555555; /* PCLK is the same as CCLK */
;;;181 PCLKSEL1 = 0x55555555;
;;;182 #endif
;;;183
;;;184 /* Set memory accelerater module*/
;;;185 MAMCR = 0;
0001f0 e3a00000 MOV r0,#0
0001f4 e5810000 STR r0,[r1,#0]
;;;186 #if Fcclk < 20000000
;;;187 MAMTIM = 1;
;;;188 #else
;;;189 #if Fcclk < 40000000
;;;190 MAMTIM = 2;
;;;191 #else
;;;192 MAMTIM = 3;
0001f8 e3a00003 MOV r0,#3
0001fc e5810004 STR r0,[r1,#4]
;;;193 #endif
;;;194 #endif
;;;195 MAMCR = 2;
000200 e3a00002 MOV r0,#2
000204 e5810000 STR r0,[r1,#0]
;;;196
;;;197 GPIOResetInit();
000208 ebfffffe BL GPIOResetInit
;;;198
;;;199 init_VIC();
00020c ebfffffe BL init_VIC
;;;200 return;
;;;201 }
000210 e8bd4010 POP {r4,lr}
000214 e12fff1e BX lr
;;;202
ENDP
|L1.536|
000218 e002c000 DCD 0xe002c000
|L1.540|
00021c 3fffc000 DCD 0x3fffc000
|L1.544|
000220 e01fc000 DCD 0xe01fc000
|L1.548|
000224 aaaaaaaa DCD 0xaaaaaaaa
AREA ||.data||, DATA, ALIGN=2
sysreg
000000 00000000 DCD 0x00000000
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