lpc23_emac.txt
来自「工厂环境污染控制数据采集器」· 文本 代码 · 共 796 行 · 第 1/3 页
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796 行
;;;366 }
;;;367 }
;;;368 MAC_MCMD = 0;
000220 e3a00000 MOV r0,#0
000224 e2403602 SUB r3,r0,#0x200000
000228 e5830024 STR r0,[r3,#0x24]
;;;369 return (MAC_MRDD);
00022c e2400602 SUB r0,r0,#0x200000
000230 e5900030 LDR r0,[r0,#0x30]
000234 e1c002c3 BIC r0,r0,r3,ASR #5
;;;370 }
000238 e12fff1e BX lr
;;;371
ENDP
write_PHY PROC
;;;338
;;;339 MAC_MADR = DP83848C_DEF_ADR | PhyReg;
00023c e3803c01 ORR r3,r0,#0x100
000240 e59fc3a8 LDR r12,|L1.1520|
000244 e58c3028 STR r3,[r12,#0x28]
;;;340 MAC_MWTD = Value;
000248 e1a0300c MOV r3,r12
00024c e583102c STR r1,[r3,#0x2c]
;;;341
;;;342 /* Wait utill operation completed */
;;;343 tout = 0;
000250 e3a02000 MOV r2,#0
;;;344 for (tout = 0; tout < MII_WR_TOUT; tout++) {
000254 e1a00000 MOV r0,r0
000258 ea000005 B |L1.628|
|L1.604|
;;;345 if ((MAC_MIND & MIND_BUSY) == 0) {
00025c e59f338c LDR r3,|L1.1520|
000260 e5933034 LDR r3,[r3,#0x34]
000264 e3130001 TST r3,#1
000268 1a000000 BNE |L1.624|
;;;346 break;
00026c ea000002 B |L1.636|
|L1.624|
000270 e2822001 ADD r2,r2,#1 ;344
|L1.628|
000274 e3520805 CMP r2,#0x50000 ;344
000278 3afffff7 BCC |L1.604|
|L1.636|
00027c e1a00000 MOV r0,r0
;;;347 }
;;;348 }
;;;349 }
000280 e12fff1e BX lr
;;;350
ENDP
init_ethernet PROC
;;;62
;;;63 void init_ethernet (void) {
000284 e92d40f0 PUSH {r4-r7,lr}
;;;64 /* Initialize the EMAC ethernet controller. */
;;;65 U32 regv,tout,id1,id2;
;;;66
;;;67 /* Power Up the EMAC controller. */
;;;68 PCONP |= 0x40000000;
000288 e59f0388 LDR r0,|L1.1560|
00028c e59000c4 LDR r0,[r0,#0xc4]
000290 e3800101 ORR r0,r0,#0x40000000
000294 e59f137c LDR r1,|L1.1560|
000298 e58100c4 STR r0,[r1,#0xc4]
;;;69
;;;70 /* Enable P1 Ethernet Pins. */
;;;71 if (MAC_MODULEID == OLD_EMAC_MODULE_ID) {
00029c e59f034c LDR r0,|L1.1520|
0002a0 e5900ffc LDR r0,[r0,#0xffc]
0002a4 e28014c7 ADD r1,r0,#0xc7000000
0002a8 e2511a22 SUBS r1,r1,#0x22000
0002ac 1a000003 BNE |L1.704|
;;;72 /* For the first silicon rev.'-' ID P1.6 should be set. */
;;;73 PINSEL2 = 0x50151105;
0002b0 e59f0364 LDR r0,|L1.1564|
0002b4 e59f1364 LDR r1,|L1.1568|
0002b8 e5810008 STR r0,[r1,#8]
0002bc ea000002 B |L1.716|
|L1.704|
;;;74 }
;;;75 else {
;;;76 /* on rev. 'A' and later, P1.6 should NOT be set. */
;;;77 PINSEL2 = 0x50150105;
0002c0 e59f035c LDR r0,|L1.1572|
0002c4 e59f1354 LDR r1,|L1.1568|
0002c8 e5810008 STR r0,[r1,#8]
|L1.716|
;;;78 }
;;;79 PINSEL3 = (PINSEL3 & ~0x0000000F) | 0x00000005;
0002cc e59f034c LDR r0,|L1.1568|
0002d0 e590000c LDR r0,[r0,#0xc]
0002d4 e3c0000f BIC r0,r0,#0xf
0002d8 e3800005 ORR r0,r0,#5
0002dc e59f133c LDR r1,|L1.1568|
0002e0 e581000c STR r0,[r1,#0xc]
;;;80
;;;81 /* Reset all EMAC internal modules. */
;;;82 MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
0002e4 e3a00ccf MOV r0,#0xcf00
0002e8 e59f1300 LDR r1,|L1.1520|
0002ec e5810000 STR r0,[r1,#0]
;;;83 MAC1_SIM_RES | MAC1_SOFT_RES;
;;;84 MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES;
0002f0 e3a00038 MOV r0,#0x38
0002f4 e5810100 STR r0,[r1,#0x100]
;;;85
;;;86 /* A short delay after reset. */
;;;87 for (tout = 100; tout; tout--);
0002f8 e3a05064 MOV r5,#0x64
0002fc ea000000 B |L1.772|
|L1.768|
000300 e2455001 SUB r5,r5,#1
|L1.772|
000304 e3550000 CMP r5,#0
000308 1afffffc BNE |L1.768|
;;;88
;;;89 /* Initialize MAC control registers. */
;;;90 MAC_MAC1 = MAC1_PASS_ALL;
00030c e3a00002 MOV r0,#2
000310 e59f12d8 LDR r1,|L1.1520|
000314 e5810000 STR r0,[r1,#0]
;;;91 MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
000318 e3a00030 MOV r0,#0x30
00031c e5810004 STR r0,[r1,#4]
;;;92 MAC_MAXF = ETH_MAX_FLEN;
000320 e3a00c06 MOV r0,#0x600
000324 e5810014 STR r0,[r1,#0x14]
;;;93 MAC_CLRT = CLRT_DEF;
000328 e59f02f8 LDR r0,|L1.1576|
00032c e5810010 STR r0,[r1,#0x10]
;;;94 MAC_IPGR = IPGR_DEF;
000330 e3a00012 MOV r0,#0x12
000334 e581000c STR r0,[r1,#0xc]
;;;95
;;;96 /* Enable Reduced MII interface. */
;;;97 MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
000338 e3a00d09 MOV r0,#0x240
00033c e5810100 STR r0,[r1,#0x100]
;;;98
;;;99 /* Reset Reduced MII Logic. */
;;;100 MAC_SUPP = SUPP_RES_RMII;
000340 e3a00b02 MOV r0,#0x800
000344 e5810018 STR r0,[r1,#0x18]
;;;101 for (tout = 100; tout; tout--);
000348 e3a05064 MOV r5,#0x64
00034c ea000000 B |L1.852|
|L1.848|
000350 e2455001 SUB r5,r5,#1
|L1.852|
000354 e3550000 CMP r5,#0
000358 1afffffc BNE |L1.848|
;;;102 MAC_SUPP = 0;
00035c e3a00000 MOV r0,#0
000360 e2401602 SUB r1,r0,#0x200000
000364 e5810018 STR r0,[r1,#0x18]
;;;103
;;;104 /* Put the DP83848C in reset mode */
;;;105 write_PHY (PHY_REG_BMCR, 0x8000);
000368 e3a01902 MOV r1,#0x8000
00036c ebfffffe BL write_PHY
;;;106
;;;107 /* Wait for hardware reset to end. */
;;;108 for (tout = 0; tout < 0x100000; tout++) {
000370 e3a05000 MOV r5,#0
000374 ea000006 B |L1.916|
|L1.888|
;;;109 regv = read_PHY (PHY_REG_BMCR);
000378 e3a00000 MOV r0,#0
00037c ebfffffe BL read_PHY
000380 e1a04000 MOV r4,r0
;;;110 if (!(regv & 0x8800)) {
000384 e3140b22 TST r4,#0x8800
000388 1a000000 BNE |L1.912|
;;;111 /* Reset complete, device not Power Down. */
;;;112 break;
00038c ea000002 B |L1.924|
|L1.912|
000390 e2855001 ADD r5,r5,#1 ;108
|L1.916|
000394 e3550601 CMP r5,#0x100000 ;108
000398 3afffff6 BCC |L1.888|
|L1.924|
00039c e1a00000 MOV r0,r0
;;;113 }
;;;114 }
;;;115
;;;116 /* Check if this is a DP83848C PHY. */
;;;117 id1 = read_PHY (PHY_REG_IDR1);
0003a0 e3a00002 MOV r0,#2
0003a4 ebfffffe BL read_PHY
0003a8 e1a06000 MOV r6,r0
;;;118 id2 = read_PHY (PHY_REG_IDR2);
0003ac e3a00003 MOV r0,#3
0003b0 ebfffffe BL read_PHY
0003b4 e1a07000 MOV r7,r0
;;;119
;;;120 if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) {
0003b8 e59f126c LDR r1,|L1.1580|
0003bc e0011007 AND r1,r1,r7
0003c0 e1810806 ORR r0,r1,r6,LSL #16
0003c4 e59f1264 LDR r1,|L1.1584|
0003c8 e1500001 CMP r0,r1
0003cc 1a00000e BNE |L1.1036|
;;;121 /* Configure the PHY device */
;;;122 #if defined (_10MBIT_)
;;;123 /* Connect at 10MBit */
;;;124 write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
;;;125 #elif defined (_100MBIT_)
;;;126 /* Connect at 100MBit */
;;;127 write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
;;;128 #else
;;;129 /* Use autonegotiation about the link speed. */
;;;130 write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
0003d0 e3a01a03 MOV r1,#0x3000
0003d4 e3a00000 MOV r0,#0
0003d8 ebfffffe BL write_PHY
;;;131 /* Wait to complete Auto_Negotiation. */
;;;132 for (tout = 0; tout < 0x100000; tout++) {
0003dc e3a05000 MOV r5,#0
0003e0 ea000006 B |L1.1024|
|L1.996|
;;;133 regv = read_PHY (PHY_REG_BMSR);
0003e4 e3a00001 MOV r0,#1
0003e8 ebfffffe BL read_PHY
0003ec e1a04000 MOV r4,r0
;;;134 if (regv & 0x0020) {
0003f0 e3140020 TST r4,#0x20
0003f4 0a000000 BEQ |L1.1020|
;;;135 /* Autonegotiation Complete. */
;;;136 break;
0003f8 ea000002 B |L1.1032|
|L1.1020|
0003fc e2855001 ADD r5,r5,#1 ;132
|L1.1024|
000400 e3550601 CMP r5,#0x100000 ;132
000404 3afffff6 BCC |L1.996|
|L1.1032|
000408 e1a00000 MOV r0,r0
|L1.1036|
;;;137 }
;;;138 }
;;;139 #endif
;;;140 }
;;;141
;;;142 /* Check the link status. */
;;;143 for (tout = 0; tout < 0x10000; tout++) {
00040c e3a05000 MOV r5,#0
000410 ea000006 B |L1.1072|
|L1.1044|
;;;144 regv = read_PHY (PHY_REG_STS);
000414 e3a00010 MOV r0,#0x10
000418 ebfffffe BL read_PHY
00041c e1a04000 MOV r4,r0
;;;145 if (regv & 0x0001) {
000420 e3140001 TST r4,#1
000424 0a000000 BEQ |L1.1068|
;;;146 /* Link is on. */
;;;147 break;
000428 ea000002 B |L1.1080|
|L1.1068|
00042c e2855001 ADD r5,r5,#1 ;143
|L1.1072|
000430 e3550801 CMP r5,#0x10000 ;143
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